EP0151694A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Logic circuit with built-in self-test function
Assignee: Toshiba Corp
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Filing: 1984-10-18
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Granted: —
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Expires: 2004-10-18
Abstract
Abstract @ A logic circuit according to this invention has a logic section (31). First input terminals of first to third EX OR gates (75, 77, 79) are respectively connected to output terminals of preselected logic elements (45, 53, 63) among the logic elements which constitute the logic section (31). Output terminals of the first and second EX OR gates (75, 77) are connected to second input terminals of the second and third EX OR gates (77, 79). The functional test for this logic circuit is performed by inputting test pattern signals to the logic section (31) and by comparing output signals of the logic section (31) and an output signal (S) of the third EX OR gate (79) with the expected values.
Inventors
- 👤 Shojiro C/O Patent Division Mori
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 23:47
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
122 words
A logic circuit having a logic section (31) including a plurality of logic elements, for receiving at least one input signal, performing a predetermined logic operation and outputting at least one signal, characterized by further comprising a detection circuit (83) for receiving a control signal (SIG), receiving the output signals of the preselected logic elements (45, 53, 63) of said logic elements and outputting a signal corresponding to the control signal (SIG) and the output signals of the preselected logic elements (45, 53, 63), thereby detecting whether the preselected logic elements (45, 53, 63) produce signals of values determined by the input signals of said logic section (31) and by the control signal (SIG), and whether said logic section (31) correctly operates.
Claim 2
Dependent Claim
122 words
A logic circuit having a logic section (31) including a plurality of logic elements, for receiving at least one input signal, performing a predetermined logic operation and outputting at least one signal, characterized by further comprising a detection circuit (83) for receiving a control signal (SIG), receiving the output signals of the preselected logic elements (45, 53, 63) of said logic elements and outputting a signal corresponding to the control signal (SIG) and the output signals of the preselected logic elements (45, 53, 63), thereby detecting whether the preselected logic elements (45, 53, 63) produce signals of values determined by the input signals of said logic section (31) and by the control signal (SIG), and whether said logic section (31) correctly operates.
Claim 3
Dependent Claim
81 words
A logic circuit according to claim 1, characterized in that said detection circuit is an exclusive OR circuit (83) connected to the output terminals of the preselected logic elements (45, 53, 63) to receive the control signal (SIG) and the output signals of the preselected logic elements (45, 53, 63), obtain the exclusive OR of the output signals of the preselected logic elements (45, 53, 63) and the control signal (SIG) and output a signal (S) corresponding to the exclusive OR.
Claim 4
Dependent Claim
99 words
A logic circuit according to claim 2, characterized in that said exclusive OR circuit (83) comprises of a plurality of exclusive OR gates (75, 77 and 79) which are connected in such a way that the output terminal of each exclusive OR gate (75, 77) is connected to a first input terminal of the succeeding exclusive OR gate (77, 79) and second input terminals are respectively connected to output terminals of the preselected logic elements (45, 53, 63) and in which the control signal (SIG) is input to a first input terminal of the front-most exclusive OR gate (75).
Claim 5
Dependent Claim
26 words
A logic circuit according to claim 2, characterized in that said exclusive OR circuit is one exclusive OR gate (129) with a plurality of input terminals.
Claim 6
Dependent Claim
105 words
A logic circuit according to claim 1, characterized in that said detection circuit comprises: a decoder (101) which inputs a selection signal and decodes the selection signal and outputs_a signal corresponding to the selection signal; gates (95, 97, 99) in which first input terminals are connected to said decoder (101) and second input- terminals are respectively connected to the preselected logic elements (45, 53, 63); and a gate circuit (83) which inputs said control signal (SIG) and is connected to said gates (95, 97, 99) and which outputs signals corresponding to said control . signal (SIG) and output signals of said gates (95, 97, 99).
Claim 7
Dependent Claim
18 words
A logic circuit according to claim 5, characterized in that said gates are AND gates (95, 97, 99).
Claim 8
Dependent Claim
18 words
A logic circuit according to claim 5, characterized in that said gates are OR gates (117, 119, 121).
Claim 9
Dependent Claim
52 words
A logic circuit according to claim 5, characterized in that said gate circuit is an OR circuit (107, 109, 111, 113) connected to the gates (95, 97, 99, 105) to output signal corresponding to the OR of the output signals of the gates (95, 97, 99, 105) and the control signal (SIG).
Claim 10
Dependent Claim
49 words
A logic circuit according to claim 5, characterized in that said gate circuit is an exclusive OR circuit (83) connected to the gate (95, 97, 99) to output signal corresponding to the exclusive OR of the output signals of the gates (95, 97, 99) and the control signal (SIG).
Claim 11
Dependent Claim
50 words
A logic circuit according to claim 5, characterized in that said gate circuit is an AND circuit (123, 125, 127) connected to the gates (117, 119, 121) to output a signal corresponding to the AND of the output signals of the gates (117, 119, 121) and the control signal (SIG).
Claim 12
Dependent Claim
25 words
A logic circuit according to claim 1, characterized in that said logic section (31) and said detection circuit (83) are formed on one semiconductor chip.
References Cited (Backward Citations)
No citation records indexed.
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