Patent US5055713A successfully refreshed from Google Patents.
US5055713A
Expired / Lapsed
US
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Output circuit of semiconductor integrated circuit
Assignee: Toshiba Corp
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Filing: 1989-11-20
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Granted: 1991-10-08
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Expires: 2009-11-20
Abstract
Abstract This invention discloses an output circuit in an integrated circuit. This invention includes first and second MOS transistors and a drive and control circuit. The first and second MOS transistors are connected in series between Vcc and Vss power source nodes, and receive complementary signals, respectively. When one of the transistors is OFF, and the other transistor is turned off from an ON state, the drive and control circuit moderately decreases a gate potential of the other transistor to a level at which a transconductance of the transistor which is turned off from an ON state is decreased to some extent. Thereafter, the drive and control circuit decreases the gate potential to a level at which the transconductance is sufficiently decreased.
Inventors
- 👤 Yuji Watanabe
- 👤 Hiroshi Sahara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 10:47
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00346; H03K19/00361
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
155 words
An output circuit for a semiconductor integrated circuit comprising: first and second power source nodes; first and second output MOS transistors coupled in series between said first and second power source nodes and controlled by respective first and second gate potentials applied thereto in accordance with first and second control signals; an output node coupled to a point between said series connected first and second output MOS transistors; control means for controlling the first and second gate potentials, said control means including means responsive to a transition of the second control signal from a high level to a low level for decreasing the gate potential of said second output transistor until a transconductance of said second output transistor is decreased to a predetermined first level, and for subsequently decreasing the gate potential of said second output transistor until the transconductance of said second transistor is decreased to a second level lower than said first level.
Claim 2
Dependent Claim
155 words
An output circuit for a semiconductor integrated circuit comprising: first and second power source nodes; first and second output MOS transistors coupled in series between said first and second power source nodes and controlled by respective first and second gate potentials applied thereto in accordance with first and second control signals; an output node coupled to a point between said series connected first and second output MOS transistors; control means for controlling the first and second gate potentials, said control means including means responsive to a transition of the second control signal from a high level to a low level for decreasing the gate potential of said second output transistor until a transconductance of said second output transistor is decreased to a predetermined first level, and for subsequently decreasing the gate potential of said second output transistor until the transconductance of said second transistor is decreased to a second level lower than said first level.
Claim 3
Dependent Claim
74 words
The output circuit according to claim 1, wherein said control means responsive to a transition of the second control signal comprises a circuit having a time constant which is determined by a capacitor and a resistor, said circuit constituting means for moderately decreasing the gate potential of said second transistor when said second control signal goes from high level to low level, and said first and second transistors are set in a high-impedance state.
Claim 4
Dependent Claim
91 words
An output circuit for an integrated circuit comprising: first and second power source nodes; first and second output MOS transistors coupled in series between said first and second power source nodes and controlled by respective first and second gate potentials applied thereto in accordance with first and second control signals; an output node coupled to a point between said series connected first and second output MOS transistors; and control means for decreasing a gate potential of said first transistor stepwise when said first transistor is turned off from an ON state.
Claim 5
Dependent Claim
91 words
An output circuit for an integrated circuit comprising: first and second power source nodes; first and second output MOS transistors coupled in series between said first and second power source nodes and controlled by respective first and second gate potentials applied thereto in accordance with first and second control signals; an output node coupled to a point between said series connected first and second output MOS transistors; and control means for decreasing a gate potential of said first transistor stepwise when said first transistor is turned off from an ON state.
Claim 6
Dependent Claim
73 words
The output circuit according to claim 3, wherein said control means includes first means for decreasing a gate potential of said first transistor at a first rate when said first signal goes from high level to low level and said first and second transistors are set in a high-impedance state, and second means for subsequently decreasing the gate potential of said first transistor at a second rate more rapid than said first rate.
Claim 7
Dependent Claim
115 words
An output circuit of an integrated circuit comprising: a first output MOS transistor comprising a plurality of MOS transistors, each of said plurality having one current path connected to a first power source node, having the other current path connected to an output node and having a gate for receiving a signal; a second output MOS transistor having one current path connected to a second power source node and the other current path connected to said output node; and control means for setting a delay time between falling edges of gate potentials of said MOS transistors which constitute said first output MOS transistor when said first MOS transistor is turned off from its ON state.
Claim 8
Dependent Claim
115 words
An output circuit of an integrated circuit comprising: a first output MOS transistor comprising a plurality of MOS transistors, each of said plurality having one current path connected to a first power source node, having the other current path connected to an output node and having a gate for receiving a signal; a second output MOS transistor having one current path connected to a second power source node and the other current path connected to said output node; and control means for setting a delay time between falling edges of gate potentials of said MOS transistors which constitute said first output MOS transistor when said first MOS transistor is turned off from its ON state.
Claim 9
Dependent Claim
77 words
The output circuit according to claim 5, wherein said control decreasing at a first rate a gate potential of said MOS transistor which is turned off first in said plurality of MOS transistors, and for decreasing at a second rate a gate potential of said MOS transistor which is turned off following said MOS transistor which is turned off first such that the second gate potential decreasing rate is higher than said first gate potential decreasing rate.
Claim 10
Dependent Claim
21 words
An output circuit according to claim 1, wherein said first and second output MOS transistors are of the same impurity type.
Claim 11
Dependent Claim
21 words
An output circuit according to claim 3, wherein said first and second output MOS transistors are of the same impurity type.
Claim 12
Dependent Claim
156 words
An output circuit for a semiconductor integrated circuit comprising: first and second power source nodes; first and second output MOS transistors coupled in series between said first and second power source nodes and controlled by respective first and second gate potentials applied thereto in accordance with first and second control signals; an output node coupled to a point between said series connected first and second output MOS transistors; and control means for controlling the first and second gate potentials, said control means including means responsive to a transition of the second control signal from a low level to a high level for increasing the gate potential of said second output transistor until a transconductance of said second output transistor is increased to a predetermined first level, and for subsequently increasing the gate potential of said second output transistor until the transconductance of said second transistor is increased to a second level higher than said first level.
Claim 13
Dependent Claim
156 words
An output circuit for a semiconductor integrated circuit comprising: first and second power source nodes; first and second output MOS transistors coupled in series between said first and second power source nodes and controlled by respective first and second gate potentials applied thereto in accordance with first and second control signals; an output node coupled to a point between said series connected first and second output MOS transistors; and control means for controlling the first and second gate potentials, said control means including means responsive to a transition of the second control signal from a low level to a high level for increasing the gate potential of said second output transistor until a transconductance of said second output transistor is increased to a predetermined first level, and for subsequently increasing the gate potential of said second output transistor until the transconductance of said second transistor is increased to a second level higher than said first level.
Claim 14
Dependent Claim
21 words
An output circuit according to claim 9, wherein said first and second output MOS transistors are of the same impurity type.
Claim 15
Dependent Claim
92 words
An output circuit for a semiconductor integrated circuit comprising: first and second power source nodes; first and second output MOS transistors coupled in series between said first and second power source nodes and controlled by respective first and second gate potentials applied thereto in accordance with first and second control signals; an output node coupled to a point between said series connected first and second output MOS transistors; and control means for increasing a gate potential of said first transistor stepwise when said first transistor is turned on from an OFF state.
Claim 16
Dependent Claim
92 words
An output circuit for a semiconductor integrated circuit comprising: first and second power source nodes; first and second output MOS transistors coupled in series between said first and second power source nodes and controlled by respective first and second gate potentials applied thereto in accordance with first and second control signals; an output node coupled to a point between said series connected first and second output MOS transistors; and control means for increasing a gate potential of said first transistor stepwise when said first transistor is turned on from an OFF state.
Claim 17
Dependent Claim
61 words
The output circuit according to claim 11, wherein said control means includes first means for increasing a gate potential of said first transistor at a first rate when said first signal goes from low level to high level, and second means for subsequently increasing the gate potential of said first transistor at a second rate less rapid than said first rate.
Claim 18
Dependent Claim
21 words
An output circuit according to claim 11, wherein said first and second output MOS transistors are of the same impurity type.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-10-07 | 1995-04-08 | 1995-10-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-10-07 | 1999-04-08 | 1999-10-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-10-07 | 2003-04-08 | 2003-10-08 | $7700.00 | Window Closed / Lapsed |