Data output circuit

Claim 2

For a semiconductor integrated circuit, a buffer circuit having a power source voltage with first and second power source terminals, an input terminal for receiving an input signal from the integrated circuit, and an output terminal for outputting an output signal in response to the input signal comprising: a plurality of transistors having first and second states coupled in parallel between said output terminal and said second power source terminal; transistor switch control means for switching each of said plurality of transistors in sequence during a switching cycle from its first state to its second state, said transistor switch control means including delay means for delaying the switching of at least one of said plurality of transistors to its second state; and transistor voltage control means for at least initially supplying a voltage to the control gate of the first transistor switched during the switching cycle which is lower than the voltage supplied to the control gates of the remaining transistors in the switching cycle.

Claim 3

The buffer circuit according to claim 1 wherein said transistor voltage control means comprises two transistors connected in series with each other and with the power source voltage.

Claim 4

The buffer circuit according to claim 2 wherein the control gate of the first transistor switched during the switching cycle is coupled to a point between the two transistors comprising the transistor voltage control means.

Claim 5

The buffer circuit according to claim 1 wherein said transistor voltage control means comprises a transistor whose control gate is coupled to the power source voltage and whose electrodes are coupled to the transistor switch control means and the control gate of the first transistor switched during the switching cycle.

Claim 6

The buffer circuit according to claim 1 further comprising a capacitor coupled between said delay means and the control gate of the first transistor switched during the switching cycle.

Claim 7

The buffer circuit according to claim 1 wherein said plurality of transistors comprises two transistors.

Claim 8

A buffer circuit for a semiconductor integrated circuit comprising: first and second power source terminals; a data output terminal; a gate circuit having an output terminal; first and second enhancement type MOS transistors connected in series between said first and second power source terminals, the control gate of said first enhancement type MOS transistor being coupled to the output terminal of said gate circuit directly, the control gate of said second enhancement type MOS transistor being coupled to the output of said gate circuit through an inverter; a third MOS transistor coupled between said data output terminal and said second power source terminal, the control gate of said third MOS transistor being coupled to a point between the series-connected first and second MOS transistors; a fourth MOS transistor coupled between the data output terminal and the second power source terminal and in parallel with said third MOS transistor; and a signal delay circuit having input and output terminals, the input terminal of said signal delay circuit being coupled to the output terminal of said gate circuit, the output terminal of said signal delay circuit being coupled to the control gate of said fourth MOS transistor, the voltage of said output terminal of said signal delay circuit when said fourth MOS transistor conducts being higher than the voltage of the point between said series-connected first and second MOS transistors when said first and second MOS transistors conduct.

Claim 9

A buffer circuit for a semiconductor integrated circuit comprising: first and second power source terminals; a data output terminal; a gate circuit having an output terminal; first and second enhancement type MOS transistors connected in series between said first and second power source terminals, the control gate of said first enhancement type MOS transistor being coupled to the output terminal of said gate circuit directly, the control gate of said second enhancement type MOS transistor being coupled to the output of said gate circuit through an inverter; a third MOS transistor coupled between said data output terminal and said second power source terminal, the control gate of said third MOS transistor being coupled to a point between the series-connected first and second MOS transistors; a fourth MOS transistor coupled between the data output terminal and the second power source terminal and in parallel with said third MOS transistor; and a signal delay circuit having input and output terminals, the input terminal of said signal delay circuit being coupled to the output terminal of said gate circuit, the output terminal of said signal delay circuit being coupled to the control gate of said fourth MOS transistor, the voltage of said output terminal of said signal delay circuit when said fourth MOS transistor conducts being higher than the voltage of the point between said series-connected first and second MOS transistors when said first and second MOS transistors conduct.

Claim 10

The buffer circuit according to claim 7 further comprising: a capacitor coupled between the output terminal of said signal delay circuit and the control gate of said third MOS transistor.

Claim 11

A buffer circuit for a semiconductor integrated circuit comprising: first and second power source terminals; a data output terminal; a gate circuit having an output terminal; a first and second MOS transistor coupled in parallel between said data output terminal and said second power source terminal; an enhancement type MOS transistor coupled between the output terminal of said gate circuit and the control gate of said first MOS transistor, the control gate of said enhancement type MOS transistor being coupled to said first power source terminal; and a signal delay circuit having input and output terminals, the input terminal of said signal delay circuit being coupled to the output terminal of said gate circuit, the output terminal of said signal delay circuit being coupled to the control gate of said second MOS transistor.

Claim 12

A buffer circuit for a semiconductor integrated circuit comprising: first and second power source terminals; a data output terminal; a gate circuit having an output terminal; a first and second MOS transistor coupled in parallel between said data output terminal and said second power source terminal; an enhancement type MOS transistor coupled between the output terminal of said gate circuit and the control gate of said first MOS transistor, the control gate of said enhancement type MOS transistor being coupled to said first power source terminal; and a signal delay circuit having input and output terminals, the input terminal of said signal delay circuit being coupled to the output terminal of said gate circuit, the output terminal of said signal delay circuit being coupled to the control gate of said second MOS transistor.

Claim 13

In a buffer circuit for a semiconductor integrated circuit, the buffer circuit having a power source voltage with first and second power source terminals, an input terminal for receiving an input signal from the integrated circuit, an output terminal for outputting an output signal in response to the input signal, and a plurality of transistors having first and second states coupled in parallel between said output terminal and said second power source terminal, a method for reducing the voltage variation of the power source voltage applied to the buffer circuit comprising the steps of: switching each of said transistors in sequence during a switching cycle from its first state to its second state; successively delaying the switching of each transistor to its second state; and supplying a lower voltage to the control gate of the first transistor switched during the switching cycle than the the voltage supplied to the control gates of the remaining transistors in the switching cycle.

Claim 14

In a buffer circuit for a semiconductor integrated circuit, the buffer circuit having a power source voltage with first and second power source terminals, an input terminal for receiving an input signal from the integrated circuit, an output terminal for outputting an output signal in response to the input signal, and a plurality of transistors having first and second states coupled in parallel between said output terminal and said second power source terminal, a method for reducing the voltage variation of the power source voltage applied to the buffer circuit comprising the steps of: switching each of said transistors in sequence during a switching cycle from its first state to its second state; successively delaying the switching of each transistor to its second state; and supplying a lower voltage to the control gate of the first transistor switched during the switching cycle than the the voltage supplied to the control gates of the remaining transistors in the switching cycle.

Claim 15

For a semiconductor integrated circuit, a buffer circuit having a power source voltage with first and second power source terminals, an input terminal for receiving an input signal from said semiconductor integrated circuit, and an output terminal for outputting an output signal in response to the input signal, said buffer circuit comprising: a plurality of transistors having first and second states coupled in parallel between said output terminal and said second power source terminal; transistor switch control means for switching each of said plurality of transistors in sequence during a switching cycle from its first state to its second state, said transistor switch control means including delay means for delaying the switching of at least one of said plurality of transistors to its second state; and transistor voltage control means for supplying a first predetermined voltage for a first predetermined period to the control gate of the first transistor switched during the switching cycle and subsequently supplying a second predetermined voltage for a second predetermined period to the control gates of the remaining transistors during the switching cycle wherein said first predetermined voltage is lower than said second predetermined voltage.

Claim 16

For a semiconductor integrated circuit, a buffer circuit having a power source voltage with first and second power source terminals, an input terminal for receiving an input signal from said semiconductor integrated circuit, and an output terminal for outputting an output signal in response to the input signal, said buffer circuit comprising: a plurality of transistors having first and second states coupled in parallel between said output terminal and said second power source terminal; transistor switch control means for switching each of said plurality of transistors in sequence during a switching cycle from its first state to its second state, said transistor switch control means including delay means for delaying the switching of at least one of said plurality of transistors to its second state; and transistor voltage control means for supplying a first predetermined voltage for a first predetermined period to the control gate of the first transistor switched during the switching cycle and subsequently supplying a second predetermined voltage for a second predetermined period to the control gates of the remaining transistors during the switching cycle wherein said first predetermined voltage is lower than said second predetermined voltage.

Claim 17

The buffer circuit according to claim 11 wherein said transistor voltage control means comprises two transistors connected in series with each other and with the power source voltage.

Claim 18

The buffer circuit according to claim 12 wherein the control gate of the first transistor switched during the switching cycle is coupled to a point between the two transistors comprising the transistor voltage control means.

Claim 19

The buffer circuit according to claim 11 wherein said transistor voltage control means comprises a transistor whose control gate is coupled to the power source voltage and whose electrodes are coupled to the transistor switch control means and the control gate of the first transistor switched during the switching cycle.

Claim 20

The buffer circuit according to claim 11 further comprising a capacitor coupled between said delay means and the control gate of the first transistor switched during the switching cycle.

Claim 21

The buffer circuit according to claim 11 wherein said plurality of transistors comprises two transistors.

Claim 22

In a buffer circuit for a semiconductor integrated circuit, the buffer circuit having a power source voltage with first and second power source terminals, an input terminal for receiving an input signal from said semiconductor integrated circuit, an output terminal for outputting an output signal in response to the input signal, and a plurality of transistors having first and second states coupled in parallel between said output terminal and said second power source terminal, a method for reducing the voltage variation of the power source voltage applied to the buffer circuit comprising the steps of: switching each of said transistors in sequence during a switching cycle from its first state to its second state; successively delaying the switching of each transistor to its second state; supplying a first predetermined voltage for a first predetermined period to the control gate of the first transistor switched during the switching cycle; and supplying a second predetermined voltage for a second predetermined period to the control gates of the remaining transistors switched during the switching cycle wherein said first predetermined voltage is less than the second predetermined voltage.

Claim 23

In a buffer circuit for a semiconductor integrated circuit, the buffer circuit having a power source voltage with first and second power source terminals, an input terminal for receiving an input signal from said semiconductor integrated circuit, an output terminal for outputting an output signal in response to the input signal, and a plurality of transistors having first and second states coupled in parallel between said output terminal and said second power source terminal, a method for reducing the voltage variation of the power source voltage applied to the buffer circuit comprising the steps of: switching each of said transistors in sequence during a switching cycle from its first state to its second state; successively delaying the switching of each transistor to its second state; supplying a first predetermined voltage for a first predetermined period to the control gate of the first transistor switched during the switching cycle; and supplying a second predetermined voltage for a second predetermined period to the control gates of the remaining transistors switched during the switching cycle wherein said first predetermined voltage is less than the second predetermined voltage.

Claim 24

For a semiconductor integrated circuit, a buffer circuit having a power source voltage with first and second power source terminals, an input terminal for receiving an input signal from said semiconductor integrated circuit, and an output terminal for outputting an output signal in response to the input signal comprising: a plurality of transistors having first and second states coupled in parallel between said output terminal and said second power source terminal; transistor switch control means for switching each of said plurality of transistors in sequence from its first state to its second state during a switching cycle, said transistor switch control means including delay means for delaying the switching of at least one of said plurality of transistors to its second state; and transistor voltage control means for initially supplying a first predetermined voltage for a first predetermined period to the control gate of the first transistor switched during the switching cycle and subsequently supplying a second predetermined voltage which is greater than said first predetermined voltage for a second predetermined period to the control gates of the remaining transistors switched during the switching cycle and raising said first predetermined voltage above said second predetermined voltage.

Claim 25

For a semiconductor integrated circuit, a buffer circuit having a power source voltage with first and second power source terminals, an input terminal for receiving an input signal from said semiconductor integrated circuit, and an output terminal for outputting an output signal in response to the input signal comprising: a plurality of transistors having first and second states coupled in parallel between said output terminal and said second power source terminal; transistor switch control means for switching each of said plurality of transistors in sequence from its first state to its second state during a switching cycle, said transistor switch control means including delay means for delaying the switching of at least one of said plurality of transistors to its second state; and transistor voltage control means for initially supplying a first predetermined voltage for a first predetermined period to the control gate of the first transistor switched during the switching cycle and subsequently supplying a second predetermined voltage which is greater than said first predetermined voltage for a second predetermined period to the control gates of the remaining transistors switched during the switching cycle and raising said first predetermined voltage above said second predetermined voltage.