Slew-rate limited output driver having reduced switching noise

Claim 2

An output circuit device which comprises: (a) first circuit means for inverting an input signal, said first circuit means having a first conductivity type MOS transistor and a second conductivity type MOS transistor connected in series to each other, the first conductivity type MOS transistor having a source connected to a first power supply and the second conductivity type MOS transistor having a source connected to a second power supply, and the first and second conductivity type MOS transistors having gates connected to an input terminal, said first circuit having an output connected to said transistors for supplying said inverted input signal as an output signal; (b) second circuit means having an output terminal for connection to a load having a parasitic capacitance, said parasitic capacitance being connectable to said output terminal such that the output signal from said first circuit means charges and discharges the parasitic capacitance, and an input and further being connected to said first circuit means for controlling a charging and discharging speed of said parasitic capacitance in accordance with a voltage of the output sinal, said second circuit means having at least a first conductivity type MOS transistor and a second conductivity type MOS transistor connected in series to each other, said second circuit means being connected between the output of said first circuit means and the output terminal, the first conductivity type MOS transistor in the second circuit means having a source connected to the first power supply, the second conductivity type MOS transistor in the second circuit means having a source connected to the second power supply; and (c) control means connected between the output of said first circuit means and the input of said second circuit means for controlling the operation of said second circuit means in accordance with the voltage of the output signal, said control means comprising NAND and NOR gates having inputs connected to each other and an inverter connected between the input terminal of said first circuit means and said connected inputs, said gates having outputs connected to said second circuit means.

Claim 3

An output circuit device which comprises: (a) first circuit means for inverting an input signal, said first circuit means having a first conductivity type MOS transistor and a second conductivity type MOS transistor connected in series to each other, the first conductivity type MOS transistor having a source connected to a first power supply and the second conductivity type MOS transistors having a source connected to a second power supply, and the first and second conductivity type MOS transistors having gates connected together to an input terminal, said first circuit having an output connected to said transistors for supplying said inverter input signal as an output signal; (b) second circuit means having an output terminal for connection to a load having a parasitic capacitance, said parasitic capacitance being connectable to said output terminal such that the output signal from said first circuit means charges and discharges the parasitic capacitance, and inputs and further being connected to said first circuit means for controlling a charging and discharging speed of said parasitic capacitance in accordance with a voltage of the output signal, said second circuit means having at least a first conductivity type MOS transistor and a second conductivity type MOS transistor connected in series to each other, said second circuit means being connected between the output of said first circuit means and the output terminal, the first conductivity type MOS transistor in the second circuit means having a source connected to the first power supply, the second conductivity type MOS transistor in said second circuit means having a source connected to the second power supply; and (c) control means connected between the output of said first circuit means and the input of said second circuit means for controlling the operation of said second circuit means in accordance with the voltage of the output signal, said control means comprising NAND and NOR gates having inputs connected to each other, a first inverter connected between the output of said first circuit means and the connected inputs of said NAND and NOR gates, and second and third inverters connected between gates of said transistors of said second circuit means and outputs of said NAND and NOR gates respectively.

Claim 4

An output circuit device which comprises: (a) first circuit means for inverting an input signal, said first circuit means having a first conductivity type MOS transistor and a second conductivity type MOS transistor connected in series to each other, the first conductivity type MOS transistor having a source connected to a first power supply and the second conductivity type MOS transistors having a source connected to a second power supply, and the first and second conductivity type MOS transistors having gates connected together to an input terminal, said first circuit having an output connected to said transistors for supplying said inverter input signal as an output signal; (b) second circuit means having an output terminal for connection to a load having a parasitic capacitance, said parasitic capacitance being connectable to said output terminal such that the output signal from said first circuit means charges and discharges the parasitic capacitance, and inputs and further being connected to said first circuit means for controlling a charging and discharging speed of said parasitic capacitance in accordance with a voltage of the output signal, said second circuit means having at least a first conductivity type MOS transistor and a second conductivity type MOS transistor connected in series to each other, said second circuit means being connected between the output of said first circuit means and the output terminal, the first conductivity type MOS transistor in the second circuit means having a source connected to the first power supply, the second conductivity type MOS transistor in said second circuit means having a source connected to the second power supply; and (c) control means connected between the output of said first circuit means and the input of said second circuit means for controlling the operation of said second circuit means in accordance with the voltage of the output signal, said control means comprising NAND and NOR gates having inputs connected to each other, a first inverter connected between the output of said first circuit means and the connected inputs of said NAND and NOR gates, and second and third inverters connected between gates of said transistors of said second circuit means and outputs of said NAND and NOR gates respectively.

Claim 5

An output circuit device which comprises: (a) first circuit means for inverting an input signal, said first circuit means having a first conductivity type MOS transistor and a second conductivity type MOS transistor connected in series to each other, the first conductivity type MOS transistor having a source connected to a first power supply and the second conductivity type MOS transistor having a source connected to a second power supply, and the first and second conductivity type MOS transistors having gates connected to an input of said first circuit means, said input of said first circuit means being connected together to an input terminal, said first circuit having an output connected to said transistors for supplying said inverted input signal as an output signal; (b) second circuit means having an output terminal for connection to a load having a parasitic capacitance, said parasitic capacitance being connectable to said output terminal such that the output signal from said first circuit means charges and discharges the parasitic capacitance, and an input and further being connected to said first circuit means for controlling a charging and discharging speed of said parasitic capacitance in accordance with a voltage of the output signal, said second circuit means having at least a first conductivity type MOS transistor and a second conductivity type MOS transistor connected in series to each other, said second circuit means being connected between the output of said first circuit means and the output terminal, the first conductivity type MOS transistor in the second circuit means having a source connectred to the first power supply, the second conductivity type MOS transistor of said second circuit means having a source connected to the second power supply; (c) control means connected between the output of said first circuit means and the input of said second circuit means for controlling the operation of said second circuit means in accordance with the voltage of the output signal, said control means comprising NAND and NOR having inputs connected to each other; and (d) an inverter having one terminal connected to the input of said first circuit means and another terminal connected to one input of said NOR gate and to said input terminal.

Claim 6

An output circuit device which comprises: (a) first circuit means for inverting an input signal, said first circuit means having a first conductivity type MOS transistor and a second conductivity type MOS transistor connected in series to each other, the first conductivity type MOS transistor having a source connected to a first power supply and the second conductivity type MOS transistor having a source connected to a second power supply, and the first and second conductivity type MOS transistors having gates connected to an input of said first circuit means, said input of said first circuit means being connected together to an input terminal, said first circuit having an output connected to said transistors for supplying said inverted input signal as an output signal; (b) second circuit means having an output terminal for connection to a load having a parasitic capacitance, said parasitic capacitance being connectable to said output terminal such that the output signal from said first circuit means charges and discharges the parasitic capacitance, and an input and further being connected to said first circuit means for controlling a charging and discharging speed of said parasitic capacitance in accordance with a voltage of the output signal, said second circuit means having at least a first conductivity type MOS transistor and a second conductivity type MOS transistor connected in series to each other, said second circuit means being connected between the output of said first circuit means and the output terminal, the first conductivity type MOS transistor in the second circuit means having a source connectred to the first power supply, the second conductivity type MOS transistor of said second circuit means having a source connected to the second power supply; (c) control means connected between the output of said first circuit means and the input of said second circuit means for controlling the operation of said second circuit means in accordance with the voltage of the output signal, said control means comprising NAND and NOR having inputs connected to each other; and (d) an inverter having one terminal connected to the input of said first circuit means and another terminal connected to one input of said NOR gate and to said input terminal.

Claim 7

An output circuit device which comprises: (a) first circuit means for inverting an input signal, said first circuit means having a first conductivity type MOS transistor and a second conductivity type MOS transistor connected in series to each other, the first conductivity type MOS transistor having a source connected to a first power supply and the second conductivity type MOS transistor having a source connected to a second power supply, and the first and second conductivity type MOS transistors having gates connected together to an input terminal, said first circuit having an output connected to said transistors for supplying said inverted input signal as an output signal; (b) second circuit means having an output terminal for connection to a load having a parasitic capacitance, said parasitic capacitance being connectable to said output terminal such that the output signal from said first circuit means charges and discharges the parasitic capacitance, and an input and further being connected to said first circuit means for controlling a charging and discharging speed of said parasitic capacitance in accordance with the voltage of the output signal, said second circuit means comprising two pairs of transistors, each pair of transistors comprising a first type MOS transistor and a second type MOS transistor connected in series with each other, the transistors of each pair having drains connected to drains of the transistors of the other pair, said second circuit means being connected between the output of said first circuit means and the output terminal, each first conductivity type MOS transistor in the second circuit means having a source connected to the first power supply, each second conductivity type MOS transistor in the second circuit means having a source connected to the second power supply; and (c)control means connected between the output of said first circuit means and the input of said second circuit means for controlling the operation of said second circuit means in accordance with a voltage of the output signal, said control means comprising two pairs of NAND and NOR gates, said NAND and NOR gate pairs having first and second switching threshold levels, respectively, and having outputs connected to gates of the first and second type MOS transistor pairs in the second circuit means; and (d) an inverter connected between the input terminal of said first circuit means and an input of each of said NAND and NOR gate pairs in the control means.

Claim 8

An output circuit device which comprises: (a) first circuit means for inverting an input signal, said first circuit means having a first conductivity type MOS transistor and a second conductivity type MOS transistor connected in series to each other, the first conductivity type MOS transistor having a source connected to a first power supply and the second conductivity type MOS transistor having a source connected to a second power supply, and the first and second conductivity type MOS transistors having gates connected together to an input terminal, said first circuit having an output connected to said transistors for supplying said inverted input signal as an output signal; (b) second circuit means having an output terminal for connection to a load having a parasitic capacitance, said parasitic capacitance being connectable to said output terminal such that the output signal from said first circuit means charges and discharges the parasitic capacitance, and an input and further being connected to said first circuit means for controlling a charging and discharging speed of said parasitic capacitance in accordance with the voltage of the output signal, said second circuit means comprising two pairs of transistors, each pair of transistors comprising a first type MOS transistor and a second type MOS transistor connected in series with each other, the transistors of each pair having drains connected to drains of the transistors of the other pair, said second circuit means being connected between the output of said first circuit means and the output terminal, each first conductivity type MOS transistor in the second circuit means having a source connected to the first power supply, each second conductivity type MOS transistor in the second circuit means having a source connected to the second power supply; and (c)control means connected between the output of said first circuit means and the input of said second circuit means for controlling the operation of said second circuit means in accordance with a voltage of the output signal, said control means comprising two pairs of NAND and NOR gates, said NAND and NOR gate pairs having first and second switching threshold levels, respectively, and having outputs connected to gates of the first and second type MOS transistor pairs in the second circuit means; and (d) an inverter connected between the input terminal of said first circuit means and an input of each of said NAND and NOR gate pairs in the control means.

Claim 9

An output circuit device which comprises: (a) first circuit means for inverting an input signal, said first circuit means having a first conductivity type MOS transistor and a second conductivity type MOS transistor connected in series to each other, the first conductivity type MOS transistor having a source connected to a first power supply and the second conductivity type MOS transistor having a source connected to a second power supply, and the first and second conductivity type MOS transistors having gates connected together to an input terminal, said first circuit having an output connected to said transistors for supplying said invertd input signal as an output signal; (b) second circuit means having an output terminal for connection to a load having a parasitic capacitance, said parasitic capacitance being connectable to said output terminal such that the output signal from said first circuit means charges and discharges the parasitic capacitance, and an input and further being connected to said first circuit means for controlling a charging and discharging speed of said parasitic capacitance in accordance with a voltage of the output signal, said second circuit means having at least a first conductivity type MOS transistor and a second conductivity type MOS transistor connected in series to each other, said second circuit means being connected between the output of said first circuit means and the output terminal, the first conductivity type MOS transistor in the second circuit means having a source connected to the first power supply, the second conductivity type MOS transistor having a source connected to the second power supply; and (c)control means connected between the output of said first circuit means and the input of said second circuit means for controlling the operation of said second circuit means in accordance with the voltage of the output signal, said control means comprising NAND and NOR gates having outputs connected, respectively, to the M0S transistors in the second circuit means, an EXCLUSIVE-0R and EXCLUSIVE-NOR gate pair having outputs connected, respectively, to inputs and said NAND and NOR gates, and an inverter connected between the input terminal of the first circuit means and a second input of said NOR gate.

Claim 10

An output circuit device which comprises: (a) first circuit means for inverting an input signal, said first circuit means having a first conductivity type MOS transistor and a second conductivity type MOS transistor connected in series to each other, the first conductivity type MOS transistor having a source connected to a first power supply and the second conductivity type MOS transistor having a source connected to a second power supply, and the first and second conductivity type MOS transistors having gates connected together to an input terminal, said first circuit having an output connected to said transistors for supplying said invertd input signal as an output signal; (b) second circuit means having an output terminal for connection to a load having a parasitic capacitance, said parasitic capacitance being connectable to said output terminal such that the output signal from said first circuit means charges and discharges the parasitic capacitance, and an input and further being connected to said first circuit means for controlling a charging and discharging speed of said parasitic capacitance in accordance with a voltage of the output signal, said second circuit means having at least a first conductivity type MOS transistor and a second conductivity type MOS transistor connected in series to each other, said second circuit means being connected between the output of said first circuit means and the output terminal, the first conductivity type MOS transistor in the second circuit means having a source connected to the first power supply, the second conductivity type MOS transistor having a source connected to the second power supply; and (c)control means connected between the output of said first circuit means and the input of said second circuit means for controlling the operation of said second circuit means in accordance with the voltage of the output signal, said control means comprising NAND and NOR gates having outputs connected, respectively, to the M0S transistors in the second circuit means, an EXCLUSIVE-0R and EXCLUSIVE-NOR gate pair having outputs connected, respectively, to inputs and said NAND and NOR gates, and an inverter connected between the input terminal of the first circuit means and a second input of said NOR gate.

Claim 11

An output circuit device which comprises: (a) first circuit means for inverting an input signal, said first circuit means having a first conductivity type MOS transistor and a second conductivity type MOS transistor connected in series to each other, the first conductivity type MOS transistor having a source connected to a first power supply and the second conductivity type MOS transistor having a source connected to a second power supply, and the first and second conductivity type MOS transistors having gates connected together to an input terminal, said first circuit having an output connected to said transistors for supplying said inverted input signal as an output signal; (b) second circuit means having an output terminal for connection to a load having a parasitic capacitance, said parasitic capacitance being connectable to said output terminal such that the output signal from said first circuit means charges and discharges the parasitic capacitance, and an input, and further being connected to said first circuit means for controlling a charging and discharging speed of said parasitic capacitance in accordance with a voltage of the output signal, said second circuit means having at least a first conductivity type MOS transistor and a second conductivity type MOS transistor connected in series to each other, said second circuit means being connected between an output of circuit means and the output terminal, the first conductivity type MOS transistor in the second circuit means having a source connecter to the first power supply, the second conductivity type MOS transistor of the second circuit means having a source connected to the second power supply; and (c) control means connected between the output of said first circuit means and the input of said second circuit means for controlling the operation of said second circuit means in accordance with the voltage of the output signal, said control means comprising NAND and NOR gates having outputs connected, respectively, to the first and second type MOS transistors of the second circuit means and having first inputs connected together and second inputs connected together, a first inverter connected between the input terminal of the first circuit means and said first inputs of said NAND and NOR gates and a second inverter connected between the output of said first circuit means and the sercond inputs of said NAND and NOR gates.

Claim 12

An output circuit device which comprises: (a) first circuit means for inverting an input signal, said first circuit means having a first conductivity type MOS transistor and a second conductivity type MOS transistor connected in series to each other, the first conductivity type MOS transistor having a source connected to a first power supply and the second conductivity type MOS transistor having a source connected to a second power supply, and the first and second conductivity type MOS transistors having gates connected together to an input terminal, said first circuit having an output connected to said transistors for supplying said inverted input signal as an output signal; (b) second circuit means having an output terminal for connection to a load having a parasitic capacitance, said parasitic capacitance being connectable to said output terminal such that the output signal from said first circuit means charges and discharges the parasitic capacitance, and an input, and further being connected to said first circuit means for controlling a charging and discharging speed of said parasitic capacitance in accordance with a voltage of the output signal, said second circuit means having at least a first conductivity type MOS transistor and a second conductivity type MOS transistor connected in series to each other, said second circuit means being connected between an output of circuit means and the output terminal, the first conductivity type MOS transistor in the second circuit means having a source connecter to the first power supply, the second conductivity type MOS transistor of the second circuit means having a source connected to the second power supply; and (c) control means connected between the output of said first circuit means and the input of said second circuit means for controlling the operation of said second circuit means in accordance with the voltage of the output signal, said control means comprising NAND and NOR gates having outputs connected, respectively, to the first and second type MOS transistors of the second circuit means and having first inputs connected together and second inputs connected together, a first inverter connected between the input terminal of the first circuit means and said first inputs of said NAND and NOR gates and a second inverter connected between the output of said first circuit means and the sercond inputs of said NAND and NOR gates.

Claim 13

An output circuit device which comprises: (a) first circuit means for inverting an input signal, said first circuit means having a first conductivity type MOS transistor and a second conductivity type MOS transistor connected in series to each other, the first conductivity type MOS transistor having a source connected to a first power supply and the second conductivity type MOS transistor having a source connected to a second power supply, and the first and second conductivity type MOS transistors having gates connected to an input terminal, said first circuit having an output connected to said transistors for supplying said inverted input signal as an output signal; (b) second circuit means having an output terminal for connection to a load having a parasitic capacitance, said parasitic capacitance being connectable to said output terminal such that the output signal from said first circuit means charges and discharges the parasitic capacitance, and an input and further being connected to said first circuit means for controlling a charging and discharging speed of said parasitic capacitance in accordance with a voltage of the output signal, said second circuit means having at least a first conductivity type MOS transistor and a second conductivity type MOS transistor connected in series to each other, said second circuit means being connected between the output of said first circuit means and the output terminal, the first conductivity type MOS transistor in the second circuit means having a source connected to the first power supply, the second conductivity type MOS transistor in the second circuit means having a source connected to the second power supply; and (c) control means connected between the output of said first circuit means and the input of said second circuit means for controlling the operation of said second circuit means in accordance with the voltage of the output signal, said control means comprising a NOR and NAND gate pair and first and second inverters connected respectively between outputs of said NOR and NAND gate pair and gates of the first and second type MOS transistors in the second circuit means, said NAND and NOR gates of said pair having one input each connected to the output of the first circuit means and another input each connected to the input terminal of the first circuit means.

Claim 14

An output circuit device which comprises: (a) first circuit means for inverting an input signal, said first circuit means having a first conductivity type MOS transistor and a second conductivity type MOS transistor connected in series to each other, the first conductivity type MOS transistor having a source connected to a first power supply and the second conductivity type MOS transistor having a source connected to a second power supply, and the first and second conductivity type MOS transistors having gates connected to an input terminal, said first circuit having an output connected to said transistors for supplying said inverted input signal as an output signal; (b) second circuit means having an output terminal for connection to a load having a parasitic capacitance, said parasitic capacitance being connectable to said output terminal such that the output signal from said first circuit means charges and discharges the parasitic capacitance, and an input and further being connected to said first circuit means for controlling a charging and discharging speed of said parasitic capacitance in accordance with a voltage of the output signal, said second circuit means having at least a first conductivity type MOS transistor and a second conductivity type MOS transistor connected in series to each other, said second circuit means being connected between the output of said first circuit means and the output terminal, the first conductivity type MOS transistor in the second circuit means having a source connected to the first power supply, the second conductivity type MOS transistor in the second circuit means having a source connected to the second power supply; and (c) control means connected between the output of said first circuit means and the input of said second circuit means for controlling the operation of said second circuit means in accordance with the voltage of the output signal, said control means comprising a NOR and NAND gate pair and first and second inverters connected respectively between outputs of said NOR and NAND gate pair and gates of the first and second type MOS transistors in the second circuit means, said NAND and NOR gates of said pair having one input each connected to the output of the first circuit means and another input each connected to the input terminal of the first circuit means.

Claim 15

An output circuit device which comprises: (a) first circuit means for inverting an input signal, said first circuit means having a first conductivity type MOS transistor and a second conductivity type MOS transistor connected in series to each other, the first conductivity type MOS transistor having a source connected to a first power supply and the second conductivity type MOS transistor having a source connected to a second power supply, and the first and second conductivity type MOS transistors having gates connected together to an input terminal, said first circuit having an output connected to said transistors for supplying said inverted input signal as an output signal; (b) second circuit means having an output terminal for connection to a load having a parasitic capacitance, said parasitic capacitance being connectable to said output terminal such that the output signal from said first circuit means charges and discharges the parasitic capacitance, and an input and further being connected to said first circuit means for controlling a charging and discharging speed of said parasitic capacitance in accordance with a voltage of the output signal, said second circuit means having at least a first conductivity type MOS transistor and a second conductivity type MOS transistor connected in series to each other, said second circuit means being connected between the output of said first circuit means and the output terminal, the first conductivity type MOS transistor in the second circuit means having a source connected to the first power supply, the second conductivity type MOS transistor in the second circuit means having a source connected to the second power supply; and (c) control means connected between the output of said first circuit means and the input of said second circuit means for controlling the operation of said second circuit means in accordance with a voltage of the output signal, said control means comprising a NAND and NOR gate pair and a first inverter, said NAND and NOR gates of said pair having outputs connected, respectively, to gates of the first and second type MOS transistors in the second circuit means, and having first inputs connected to each other and to an output of said first inverter, and second inputs connected to other; and (d) a second inverter connected between the gates of the transistors of said first circuit means and the input terminal which is in turn connected to said connected second inputs of said NAND and NOR gate pair.

Claim 16

An output circuit device which comprises: (a) first circuit means for inverting an input signal, said first circuit means having a first conductivity type MOS transistor and a second conductivity type MOS transistor connected in series to each other, the first conductivity type MOS transistor having a source connected to a first power supply and the second conductivity type MOS transistor having a source connected to a second power supply, and the first and second conductivity type MOS transistors having gates connected together to an input terminal, said first circuit having an output connected to said transistors for supplying said inverted input signal as an output signal; (b) second circuit means having an output terminal for connection to a load having a parasitic capacitance, said parasitic capacitance being connectable to said output terminal such that the output signal from said first circuit means charges and discharges the parasitic capacitance, and an input and further being connected to said first circuit means for controlling a charging and discharging speed of said parasitic capacitance in accordance with a voltage of the output signal, said second circuit means having at least a first conductivity type MOS transistor and a second conductivity type MOS transistor connected in series to each other, said second circuit means being connected between the output of said first circuit means and the output terminal, the first conductivity type MOS transistor in the second circuit means having a source connected to the first power supply, the second conductivity type MOS transistor in the second circuit means having a source connected to the second power supply; and (c) control means connected between the output of said first circuit means and the input of said second circuit means for controlling the operation of said second circuit means in accordance with a voltage of the output signal, said control means comprising a NAND and NOR gate pair and a first inverter, said NAND and NOR gates of said pair having outputs connected, respectively, to gates of the first and second type MOS transistors in the second circuit means, and having first inputs connected to each other and to an output of said first inverter, and second inputs connected to other; and (d) a second inverter connected between the gates of the transistors of said first circuit means and the input terminal which is in turn connected to said connected second inputs of said NAND and NOR gate pair.

Claim 17

An outut circuit device which comprises: (a) first circuit means for inverting an input signal, said first circuit means having a first conductivity type MOS transistor and a second conductivity type MOS transistor connected in series to each other, the first conductivity type MOS transistor having a source connected to a first power supply and the second conductivity type MOS transistor having a source connected to a second power supply, and the first and second conductivity type MOS transistors having gates connected, respectively, to input terminals, said first circuit having an output connected to said transistors for supplying said inverted input signal as an output signal; (b) second circuit means having an output terminal for connection to a load having a parasitic capacitance, said parasitic capacitance being connectable to said output terminal such that the output signal from said first circuit means charges and discharges the parasitic capacitance an, and input and further being connected to said first circuit means for controlling a charging and discharging speed of said parasitic capacitance in accordance with a voltage of the output signal, said second circuit means having at least a first conductivity type MOS transistor and a second conductivity type MOS transistor connected in series to each other, said second circuit means being connected between the output of said first circuit means and the output terminal, the first conductivity type MOS transistor in the second circuit means having a source connected to the first power supply, the second conductivity type MOS transistor in the second circuit means having a source connected to the second power supply; and (c) control means connected between the output of said first circuit means and the input of said second circuit means for controlling the operation of said second circuit means in accordance with the voltage of the output signal, said control means comprising a NAND and NOR gate pair and first and second inverters, said NAND and NOR gates of said pair having inputs connected to each other and to the output of the first circuit means, and having outputs connected to gates of the first and second type MOS transistors in the second circuit means, and said first and second inverters having inputs connected, respectively, to said input terminals, and having outputs connected, respectively, to second inputs of said NAND and NOR gates.

Claim 18

An outut circuit device which comprises: (a) first circuit means for inverting an input signal, said first circuit means having a first conductivity type MOS transistor and a second conductivity type MOS transistor connected in series to each other, the first conductivity type MOS transistor having a source connected to a first power supply and the second conductivity type MOS transistor having a source connected to a second power supply, and the first and second conductivity type MOS transistors having gates connected, respectively, to input terminals, said first circuit having an output connected to said transistors for supplying said inverted input signal as an output signal; (b) second circuit means having an output terminal for connection to a load having a parasitic capacitance, said parasitic capacitance being connectable to said output terminal such that the output signal from said first circuit means charges and discharges the parasitic capacitance an, and input and further being connected to said first circuit means for controlling a charging and discharging speed of said parasitic capacitance in accordance with a voltage of the output signal, said second circuit means having at least a first conductivity type MOS transistor and a second conductivity type MOS transistor connected in series to each other, said second circuit means being connected between the output of said first circuit means and the output terminal, the first conductivity type MOS transistor in the second circuit means having a source connected to the first power supply, the second conductivity type MOS transistor in the second circuit means having a source connected to the second power supply; and (c) control means connected between the output of said first circuit means and the input of said second circuit means for controlling the operation of said second circuit means in accordance with the voltage of the output signal, said control means comprising a NAND and NOR gate pair and first and second inverters, said NAND and NOR gates of said pair having inputs connected to each other and to the output of the first circuit means, and having outputs connected to gates of the first and second type MOS transistors in the second circuit means, and said first and second inverters having inputs connected, respectively, to said input terminals, and having outputs connected, respectively, to second inputs of said NAND and NOR gates.

Claim 19

An output circuit device as claimed in claim 9, wherein said control means further comprises a third inverter connected between the output of the first circuit means and the connected inputs of said NAND and NOR gates.

Claim 20

An output circuit device which comprises: (a) first circuit means for inverting an input signal from an input terminal and supplying the inverted input signal as an output signal; (b) second circuit means having an output terminal for connection to a load having a parasitic capacitance, said parasitic capacitance being connectable to said output terminal such that the output signal from said first circuit means charges and discharges the parasitic capacitance, and an input and further being connected to said first circuit means for controlling a charging and discharging speed of the parasitic capacitance in accordance with a voltage of the output signal to suppress a transient current generated at the time of charging and discharging the parasitic capacitance; and (c) control means connected between the output of said first circuit means, the input of said second circuit means and said input terminal for controlling the operation of said second circuit means in accordance with the voltage of the output signal and the input signal.

Claim 21

An output circuit device which comprises: (a) first circuit means for inverting an input signal from an input terminal and supplying the inverted input signal as an output signal; (b) second circuit means having an output terminal for connection to a load having a parasitic capacitance, said parasitic capacitance being connectable to said output terminal such that the output signal from said first circuit means charges and discharges the parasitic capacitance, and an input and further being connected to said first circuit means for controlling a charging and discharging speed of the parasitic capacitance in accordance with a voltage of the output signal to suppress a transient current generated at the time of charging and discharging the parasitic capacitance; and (c) control means connected between the output of said first circuit means, the input of said second circuit means and said input terminal for controlling the operation of said second circuit means in accordance with the voltage of the output signal and the input signal.

Claim 22

An output circuit device as claimed in claim 11, wherein said control means comprises NAND and NOR gates having inputs connected to each other and an inverter connected between the input terminal of said first circuit means and said connected inputs.