US3909633A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Wide bandwidth solid state input buffer
Assignee: Motorola Solutions Inc
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Filing: 1974-12-05
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Granted: 1975-09-30
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Expires: 1994-12-05
Abstract
Abstract An input buffer circuit provides a series of output electronic pulses, substantially identical to each other and having relatively fast rise and fall times, even though the input pulses to the buffer may be unlike each other and have relatively slow rise and fall times. A first inverter receives and inverts the input pulses while a second inverter provides the uniform output pulses. A first latching circuit, comprised of a third and fourth inverter first opposes and then changes state to aid the inversion of a pulse by the first inverter resulting in a net speed-up of inversion. A second latching circuit first opposes and then changes state to aid the inversion, in the opposite direction, of a pulse by the first inverter resulting in a net speed-up of inversion in the opposite direction. The two latching circuits thereby provide an inverted pulse to the second inverter that has fast fall and rise time. This inverted pulse is nearly independent of the input pulse, except as to the triggering function of the first inverter, therefore, the pulses out of the second inverter are substantially identical.
Inventors
- 👤 Ii David Wilson Hall
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 09:23
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/017; H03K19/01707; H03K19/01721; H03K5/00; H03K5/01; H03K5/12
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
210 words
A signal shaping circuit comprising: a. a common node; b. input means adapted to receive an input signal, said input means being responsive to the input signal changing states at first or second transition times to either a first or a second digital level for applying either first or second transition voltage signals, respectively, to said first common node; c. first and second threshold switching device means coupled to said first common node, said first and second threshold switching device means each being responsive to first or second voltage levels, respectively, for changing states; d. third output threshold switching device means coupled to said first common node and being responsive to a third voltage level for changing states, said third voltage level being intermediate to said first and second voltage levels; e. said first threshold switching device means being responsive during a first portion of said first transition voltage signal for supplying current in one direction for opposing said first transition voltage signal in going from said first to said second digital level, and being responsive during a second portion of said first transition voltage signal for sinking current in an opposite direction for assisting said first transition voltage signal in going from said first to said second digital level.
Claim 2
Dependent Claim
210 words
A signal shaping circuit comprising: a. a common node; b. input means adapted to receive an input signal, said input means being responsive to the input signal changing states at first or second transition times to either a first or a second digital level for applying either first or second transition voltage signals, respectively, to said first common node; c. first and second threshold switching device means coupled to said first common node, said first and second threshold switching device means each being responsive to first or second voltage levels, respectively, for changing states; d. third output threshold switching device means coupled to said first common node and being responsive to a third voltage level for changing states, said third voltage level being intermediate to said first and second voltage levels; e. said first threshold switching device means being responsive during a first portion of said first transition voltage signal for supplying current in one direction for opposing said first transition voltage signal in going from said first to said second digital level, and being responsive during a second portion of said first transition voltage signal for sinking current in an opposite direction for assisting said first transition voltage signal in going from said first to said second digital level.
Claim 3
Dependent Claim
88 words
A signal shaping circuit as in claim 1 wherein: a. said second threshold switching device means being responsive during a first portion of said second transition voltage signal for supplying current in one direction for opposing said second transition voltage signal in going from said second to said first digital level and, being responsive during a second portion of said second transition voltage signal for sinking current in an opposite direction for assisting said second transition voltage signal in going from said second to said first digital level.
Claim 4
Dependent Claim
43 words
A signal shaping circuit as in claim 2 wherein: a. said input means includes impedance means having a value for insuring that said first, second and third output threshold switching device means switch states at their respective first, second, and third voltage levels.
Claim 5
Dependent Claim
72 words
A signal shaping circuit as in claim 3 wherein: a. said first threshold switching device means comprises a first closed loop including first MOS and second MOS serially interconnected inverter circuits; b. saie second threshold switching device means comprise a second closed loop including third MOS and fourth MOS serially interconnected inverter circuits; and c. said first and second threshold switching device means being connected in parallel to said first common node.
Claim 6
Dependent Claim
32 words
A signal shaping circuit as in claim 4 wherein: a. said first and third inverter MOS circuits each constitute voltage threshold switching devices responsive to said first and second voltage levels, respectively.
Claim 7
Dependent Claim
25 words
A signal shaping circuit as in claim 4 wherein: a. said second and fourth MOS inverter circuits constitute first and second reversible current generators, respectively.
Claim 8
Dependent Claim
30 words
A signal shaping circuit as in claim 3 wherein: a. said first and second threshold switching device means and said third output threshold switching device means each comprise CMOS devices.
Claim 9
Dependent Claim
22 words
A signal shaping circuit as in claim 3 wherein: a. said first and second threshold switching device means each comprise CMOS devices.
Claim 10
Dependent Claim
17 words
A signal shaping circuit as in claim 7 wherein: a. said input means comprises a CMOS device.
Claim 11
Dependent Claim
33 words
A signal shaping circuit as in claim 4 wherein: a. said input means and said third output threshold switching device means each comprises a MOS fifth and a MOS sixth inverter circuit, respectively.
Claim 12
Dependent Claim
22 words
A signal shaping circuit as in claim 4 wherein: a. said first, second, third and fourth inverter circuits each comprise CMOS devices.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-09-29 | 1979-03-31 | 1979-09-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-09-29 | 1983-03-31 | 1983-09-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-09-29 | 1987-03-31 | 1987-09-30 | $7700.00 | Window Closed / Lapsed |