Metal oxide semiconductor (mos) hysteresis circuits

Claim 2

A transistor circuit comprising: a. a potential source; b. an input terminal and an output terminal, c. a first field effect transistor, the gate thereof connected to said input terminal; d. a second field effect transistor, the gate and drain thereof connected to said potential source, the source thereof connected to the drain of said first transistor e. a third field effect transistor, the gate and drain thereof connected to said potential source; f. a fourth field effect transistor, the gate thereof connected to said potential source, the drain connected to the source of said third transistor and the source thereof connected to a common reference point; g. a fifth field effect transistor, the drain thereof connected to the source of said first transistor and the source of said third transistor, the source thereof connected to a common reference point; h. a sixth field effect transistor, the gate thereof connected to the source of said second transistor, the drain connected to said potential source; i. a seventh field effect transistor, the drain thereof connected to the source of said sixth transistor, the gate electrode connected to the drain of said third transistor, and the source thereof connected to a common reference point; j. an eighth transistor, the drain and gate thereof connected to said potential source, the source connected to said output terminal and to the gate of said fifth transistor; and k. a ninth field effect transistor, the drain thereof connected to said output terminal, the gate connected to the drain of said seventh transistor and the source of said sixth transistor and the source connected to said common reference point.

Claim 3

A transistor circuit comprising: a. a potential source; b. an input terminal and an output terminal; c. a first field effect transistor, the gate thereof connected to said input terminal, the drain connected to said potential source; d. a second field effect transistor with the gate thereof connected to said potential source, the source connected to the source of said first transistor and the source connected to a common reference point. e. a third field effect transistor, the drain and gate thereof connected to said potential source; f. a fourth field effect transistor, the gate thereof connected to said input terminal, the drain connected to the source of said third transistor; g. a fifth field effect transistor, the gate thereof connected to the drain of said second transistor, the draIn connected to the drain of said fourth transistor and the source connected to a common reference point; h. a sixth field effect transistor, the drain thereof connected to the source of said fourth transistor and the source connected to a common reference point; i. a seventh field effect transistor, the gate and drain thereof connected to said potential source, the source connected to said output terminal and to the gate of said sixth transistor; and j. an eighth field effect transistor, the gate thereof connected to the drain of said fourth transistor, the drain connected to said output terminal, and the source connected to a common reference point

Claim 4

A digital circuit for generating a first output voltage level in response to a first voltage level of an input pulse and a second output voltage level in response to a later occurring and lesser second voltage level of the input pulse, said first and second voltage levels of said input being between the extreme voltage levels of said input pulse, said circuit comprising, first detector means responsive to the voltage levels of said input pulse for generating a control voltage as a function of the first and second voltage levels of said input pulse, second means responsive to said control voltage for generating said output voltage levels, third means receiving a feedback from the output control, said first and third means including switchable impedance meAns being connected in electrical parallel with each other for generating said control voltage as a function of the parallel impedance of said first and third means, said impedance being at least partially controlled by said feedback. 6 .The digital circuit recited in claim 5 wherein said first detector means comprises first and second field effect transistors connected in series, said control voltage being generated at a point between said series connected field effect transistors, said first field effect transistor receiving said input pulse, and said third means comprising a third field effect transistor connected in electrical parallel with said second field effect transistor, said third field effect transistor having a gate electrode connected to said output for receiving said feedback, said feedback switching the impedance of the parallel combination of said second and third field effect transistors for controlling the control voltage level at the point between said first and second field effect transistors.

Claim 5

The digital circuit recited in claim 5 wherein said fist detector means comprises first and second field effect transistors connected in electrical parallel and having a common connection for providing said control voltage to said second means, and said third means comprising a third field effect transistor connected in electrical series with said first field effect transistor and having a gate electrode connected to receive the feedback from said output for switching the impedance of said first and third field effect transistors connected in electrical parallel with said second controlling field effect transistor control voltage level at said common connection.

Claim 6

The digital circuit recited in claim 7 wherein said first detector means further comprises a fourth field effect transistor connected between the input and the gate electrode of said second field effect transistor for determining the first voltage level of the input pulse at which said digital circuit responds, said first field effect transistor having its gate electrode connected to said input for determining the second voltage level of the input pulse at which said digital circuit responds, and said second means comprising a fifth field effect transistor having its gate electrode connected to said common point for receiving said control voltage.