US4518880A
Expired / Lapsed
US
⏱️ 0.0 years remaining
MOS Switch circuit with consistent low on resistance
Assignee: Toshiba Corp
•
Filing: 1983-02-25
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Granted: 1985-05-21
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Expires: 2003-02-25
Abstract
Abstract The invention provides an inverting amplifier having a CMOS inverter and a MOSFET, the latter being connected to an input-output path of the CMOS inverter to autozero the CMOS inverter to its toggle point upon being turned on. An output signal from a CMOS inverter which has a short-circuited input-output path is supplied to the back gate of the MOSFET. Even if a gate threshold voltage of the MOSFET varies, its ON resistance is kept substantially constant.
Inventors
- 👤 Eiji Masuda
- 👤 Kenji Matsuo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 14:55
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/22; H03K5/24; H03K5/2472; H03K5/249; H03K17/00; H03K17/06; H03K17/51; H03K17/56; H03K17/687; H03K17/6871; H03K17/6872; H03K19/00; H03K19/003; H03K19/00369; H03K19/00384; H03K2217/00; H03K2217/0018
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
112 words
An MOS switch circuit with low ON resistance with low-variation, which comprises: a first MOS transistor switch having source and drain electrodes connected to input and output terminals of the switch circuit, respectively, and also having gate and back gate electrodes, the on/off state of the first MOS transistor switch being controlled by a control signal supplied to the gate electrode thereof; and biasing means, including a second MOS transistor switch having a channel type the same as the channel type of the first MOS transistor switch, for supplying a voltage corresponding to a threshold voltage of the second MOS transistor switch to the back gate of the first MOS transistor switch.
Claim 2
Dependent Claim
112 words
An MOS switch circuit with low ON resistance with low-variation, which comprises: a first MOS transistor switch having source and drain electrodes connected to input and output terminals of the switch circuit, respectively, and also having gate and back gate electrodes, the on/off state of the first MOS transistor switch being controlled by a control signal supplied to the gate electrode thereof; and biasing means, including a second MOS transistor switch having a channel type the same as the channel type of the first MOS transistor switch, for supplying a voltage corresponding to a threshold voltage of the second MOS transistor switch to the back gate of the first MOS transistor switch.
Claim 3
Dependent Claim
96 words
A circuit according to claim 1, in which said biasing means is a CMOS inverter having output and input terminals, the CMOS inverter being formed of the second MOS transistor switch and a third MOS transistor switch having a channel type opposite to the channel type of the second MOS transistor switch, the second and the third MOS transistor switches being connected in series between first and second reference voltage terminals, the output terminal and the input terminal of the CMOS inverter being short-circuited and connected to the back gate of the first MOS transistor switch.
Claim 4
Dependent Claim
71 words
A circuit according to claim 1, in which said biasing means comprises a series combination of a constant current source and the second MOS transistor switch connected between first and second reference voltage terminals, the gate of the second MOS transistor switch being connected to the junction between the constant current source and the second MOS transistor switch and further connected to the back gate of the first MOS transistor switch.
Claim 5
Dependent Claim
15 words
A circuit according to claim 3, in which said constant current source is a resistor.
Claim 6
Dependent Claim
98 words
A circuit according to claim 1, wherein said first MOS transistor switch comprises a CMOS transistor switch formed of a MOSFET, and said biasing means comprises two CMOS inverters each formed of the second MOS transistor switch and a third MOS transistor switch which has a channel type opposite to the channel type of the second MOS transistor switch, the second and the third MOS transistor switches being connected in series between first and second reference voltage terminals, the output and input terminals of the CMOS inverter being short-circuited and connected to the back gate of the MOSFET.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-05-20 | 1988-11-19 | 1989-05-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-05-20 | 1992-11-19 | 1993-05-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-05-20 | 1996-11-19 | 1997-05-21 | $7700.00 | Window Closed / Lapsed |