FET gating circuit for switching electrical loads

Claim 2

Circuit arrangement for switching an electrical load, comprising an MOS switching transistor having its drain-source path connected between the positive terminal of a d-c voltage source and one side of the load, the other side of the load being connected to ground potential, said switching transistor having a gate to which a control voltage is applied which is at least equal to the sum of the voltage of said d-c voltage source and a voltage of a gate-source path of said switching transistor, an oscillator circuit for generating said control voltage by voltage transformation, said oscillator circuit being connected in parallel with said series connection of the load and said switching transistor between said positive and negative terminals of said d-c voltage source, and an input transistor for switching said switching transistor, said input transistor having a drain-source path connecting said gate of said switching transistor and said negative terminal of said d-c voltage source, said input transistor having a gate for receiving switching pulses.

Claim 3

Circuit arrangement according to claim 1, wherein said oscillator circuit is formed of a ferrite core with three windings, a capacitor, first and second resistors and a transistor, the first resistor being connected at one end with the positive terminal of the d-c source and at the other end in series with one side of the capacitor, the other side of the capacitor being connected to ground potential, one end of the first winding being connected to a point connecting said other end of the first resistor and said one side of the capacitor, the other end of the first winding being connected to a base of the transistor, the second resistor being connected at one end with the positive terminal of the d-c source and at the other end with one end of the second winding, the other end of the second winding being connected through a collector-emitter path of the transistor to ground potential, one end of the third winding being connected with ground potential, another capacitor being connected at one side to the other end of the third winding via a rectifier diode, said other capacitor having its other side connected to ground potential, said control voltage (U ST ) being obtainable across said other capacitor.

Claim 4

Circuit arrangement according to claim 1, wherein the electrical load is formed of a plurality of individual loads, a respective switching transistor and a respective input transistor being provided for each of said individual loads.