US4052623A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Isolated semiconductor gate control circuit
Assignee: General Electric Co
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Filing: 1976-08-10
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Granted: 1977-10-04
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Expires: 1996-08-10
Abstract
Abstract A circuit for the generation or development of a gating signal for a semiconductor device which is isolated from the circuit of the device itself is comprised of a pulse generating section which feeds pulses to the primary winding of a transformer to thereby induce pulses into the transformer secondary winding. An output section is connected to the secondary winding of the transformer which provides alternately, relatively positive and negative going output signals which serve as the gating signals for the semiconductor device. As provided in the preferred embodiment, the semiconductor device is a field effect transistor and the output section insures that during times in which it is desired to have the transistor conducting, a relatively positive pulse is applied to the gate electrode of the field effect transistor while during periods between pulses, when it is desired to have the transistor non-conducting, there is a sufficiently negative signal applied to the gate electrode so as to maintain the field effect transistor in its nonconducting state.
Inventors
- 👤 Hans O. Loberg
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 06:17
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/687; H03K17/689; H03K17/691; H03K17/60; H03K17/601; H03K17/06; H03K2017/066
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
140 words
An isolated gate control for a voltage controlled semiconductor device responsive to gate signals to be thereby alternately rendered conductive and nonconductive comprising: a. pulse generating means to provide a train of pulses at a frequency corresponding to the desired operational rate of the semiconductor device; b. a transformer having primary and secondary windings; c. means for connecting said pulse generating means to said primary winding whereby a pulse is induced into said secondary winding; and, d. an output circuit connected to said secondary winding, said circuit including means for alternately providing relatively positive and negative going output voltage signals serving as gate signals to the semiconductor device, each of said output signals having minimum prescribed absolute voltage values during periods corresponding to, respectively, the period of the pulses of said train and the period of time between adjacent pulses.
Claim 2
Dependent Claim
140 words
An isolated gate control for a voltage controlled semiconductor device responsive to gate signals to be thereby alternately rendered conductive and nonconductive comprising: a. pulse generating means to provide a train of pulses at a frequency corresponding to the desired operational rate of the semiconductor device; b. a transformer having primary and secondary windings; c. means for connecting said pulse generating means to said primary winding whereby a pulse is induced into said secondary winding; and, d. an output circuit connected to said secondary winding, said circuit including means for alternately providing relatively positive and negative going output voltage signals serving as gate signals to the semiconductor device, each of said output signals having minimum prescribed absolute voltage values during periods corresponding to, respectively, the period of the pulses of said train and the period of time between adjacent pulses.
Claim 3
Dependent Claim
41 words
The invention in accordance with claim 1 in which the semiconductor device is a field effect transistor and wherein said relatively positive going output signals serve to render said transistor conductive and said relatively negative going pulses render said transistor nonconductive.
Claim 4
Dependent Claim
139 words
A circuit for generating isolated gate signals for controlling the conductive state of a field effect transistor comprising: a. a pulse generating means for providing a train of pulses at a frequency corresponding to the desired operational rate of said tansistor; b. a transformer having primary and secondary windings; c. means for connecting said pulse generating means to said primary winding whereby a pulse is induced into said secondary winding; and, d. an output circuit connected to said secondary winding for providing relatively positive and negative signals serving as said gate signals, said output circuit including a diode and a resistor-capacitor network, said resistor-capacitor network having a time constant of adequate duration to maintain the gate signal at a level sufficient in magnitude to maintain the transistor in the nonconducting state during the time between pulses from said generator.
Claim 5
Dependent Claim
139 words
A circuit for generating isolated gate signals for controlling the conductive state of a field effect transistor comprising: a. a pulse generating means for providing a train of pulses at a frequency corresponding to the desired operational rate of said tansistor; b. a transformer having primary and secondary windings; c. means for connecting said pulse generating means to said primary winding whereby a pulse is induced into said secondary winding; and, d. an output circuit connected to said secondary winding for providing relatively positive and negative signals serving as said gate signals, said output circuit including a diode and a resistor-capacitor network, said resistor-capacitor network having a time constant of adequate duration to maintain the gate signal at a level sufficient in magnitude to maintain the transistor in the nonconducting state during the time between pulses from said generator.
Claim 6
Dependent Claim
40 words
The invention in accordance with claim 3 wherein said pulse generating means develops positive going pulses in said secondary winding and said diode serves to conduct positive going pulses to thereby gate said field effect transistor into the conducting state.
Claim 7
Dependent Claim
19 words
The invention in accordance with claim 4 wherein the gate signals are derived from the voltage across said diode.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-10-03 | 1981-04-04 | 1981-10-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-10-03 | 1985-04-04 | 1985-10-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-10-03 | 1989-04-04 | 1989-10-04 | $7700.00 | Window Closed / Lapsed |