Buffer circuit for minimizing noise in an integrated circuit

Claim 1

A buffer circuit for an integrated circuit device having an in-chip power source potential and an in-chip ground potential, the buffer circuit comprising: a power source node electrically connected to the in-chip power source potential; a ground node electrically connected to the in-chip ground potential; first and second input nodes for receiving input signals from the integrated device; an output node for outputting the output current from the buffer circuit; load transistor means connected to the first input node for controlling the output current to the output node; drive transistor means connected to the second input node for controlling the output current to the output node; a first buffering transistor connected in series with said load transistor means; and a second buffering transistor connected in series with said drive transistor means and said first buffering transistor, said first and second buffering transistors stabilizing the in-chip power source and ground potential of the device by suppressing fluctuations in the amplitude of the output current and defining said output node therebetween.