US4275313A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Current limiting output circuit with output feedback
Assignee: AT&T Inc
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Filing: 1979-04-09
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Granted: 1981-06-23
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Expires: 1999-04-09
Abstract
Abstract An IGFET push-pull driver circuit includes an output stage having pull-up and pull-down IGFETs for driving an output node. An inverter stage drives the gate of the pull-up IGFET. A current sensing IGFET biased to represent a resistance is coupled between the pull-up IGFET and the output node to provide a voltage drop which is proportional to the current flowing through the pull-up IGFET. A regulating IGFET with its channel coupled between the gate of the pull-up IGFET and the output node and with its gate coupled to the juncture of the pull-up IGFET and the current sensing IGFET, responds to the voltage drop across the current sensing IGFET to provide feedback control of the conductance of the pull-up IGFET. The maximum output current of the driver is limited to a value which remains substantially constant over a wide range of processing parameters, operating temperature and load impedance.
Inventors
- 👤 Harry J. Boll
- 👤 Richard M. Goldstein
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 05:37
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/003; H03K19/00315
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
130 words
A current limiting push-pull driver circuit comprising: a first IGFET having its channel coupled between a first voltage conductor and an output node, the gate of the first IGFET being coupled to first input signal means, a second IGFET having its channel coupled between a second voltage conductor and a control node, the gate of the second IGFET being coupled to second input signal means complementary to the first, characterized in that there are included current sensing means coupled between the control node and the output node for producing a sensing voltage proportional to the current flowing between the second voltage conductor and the output node, and regulating means coupled to the gate of the second IGFET responsive to the sensing voltage for altering the conductance of the second IGFET.
Claim 2
Dependent Claim
130 words
A current limiting push-pull driver circuit comprising: a first IGFET having its channel coupled between a first voltage conductor and an output node, the gate of the first IGFET being coupled to first input signal means, a second IGFET having its channel coupled between a second voltage conductor and a control node, the gate of the second IGFET being coupled to second input signal means complementary to the first, characterized in that there are included current sensing means coupled between the control node and the output node for producing a sensing voltage proportional to the current flowing between the second voltage conductor and the output node, and regulating means coupled to the gate of the second IGFET responsive to the sensing voltage for altering the conductance of the second IGFET.
Claim 3
Dependent Claim
79 words
A driver circuit as recited in claim 1 wherein the second input signal means comprise an inverter circuit having a third IGFET having its channel coupled between the first voltage conductor and a second node, the gate of the third IGFET being coupled to the first input signal means, a fourth IGFET having its channel coupled between a third voltage conductor and the second node, and wherein the gate of the second IGFET is coupled to the second node.
Claim 4
Dependent Claim
40 words
A driver circuit as recited in claim 2 wherein the regulating means comprises a fifth IGFET having its channel coupled between the second node and the output node, the gate of the fifth IGFET being coupled to the control node.
Claim 5
Dependent Claim
25 words
A driver circuit as recited in claim 3 wherein the current sensing means comprises a resistor coupled between the control node and the output node.
Claim 6
Dependent Claim
59 words
A circuit as recited in claim 3 wherein the current sensing means comprises a sixth IGFET having its channel coupled between the control node and the output node, and where the maximum current flowing between the second voltage conductor and the output node is determined by a relationship among the transconductances of the second, third, fifth and sixth IGFETs.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-06-22 | 1984-12-22 | 1985-06-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-06-22 | 1988-12-22 | 1989-06-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-06-22 | 1992-12-22 | 1993-06-23 | $7700.00 | Window Closed / Lapsed |