Patent US4945067A successfully refreshed from Google Patents.
US4945067A
Expired / Lapsed
US
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Intra-gate offset high voltage thin film transistor with misalignment immunity and method of its fabrication
Assignee: Xerox Corp
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Filing: 1989-11-02
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Granted: 1990-07-31
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Expires: 2009-11-02
Abstract
Abstract A high voltage thin film transistor comprising a substrate upon which is supported a non-single crystal semiconductor active layer, spaced from a pair of conductive gate electrodes by a gate dielectric layer, wherein one of the gate electrodes in the device control electrode and the other is a dummy-drain electrode. Heavily doped semiconductor source and drain electrodes are in substantial alignment with the outer edges of the gate electrodes, the source electrode being aligned with the device control electrode and the drain electrode being aligned with the dummy-drain electrode. The active layer has intrinsic or virtually intrinsic regions thereof in opposition to the bodies of each of the gate electrodes, and an offset region, between the gate electrodes, having a lower depant level than the source and drain electrodes, which is aligned with the inner edges of the gate electrodes.
Inventors
- 👤 Tiao-Yuan Huang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 18:50
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0321; H10D30/60; H10D30/611; H10D30/67; H10D30/6729; H10D30/673; H10D30/6733; H10D30/674; H10D64/00; H10D64/01; H10D64/031; H10D64/035
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
131 words
A process for forming a high voltage thin film transistor comprising the steps of depositing an intrinsic non-single crystal semiconductor layer upon a dielectric substrate, depositing a gate dielectric layer over said intrinsic semiconductor layer, depositing a conductive layer over said gate dielectric layer, patterning said conductive layer with a single mask to form a pair of gate electrodes with a precise distance therebetween, implanting lightly doped regions in said semiconductor layer, using said gate electrodes as an implantation mask, so as to dope those regions of said semiconductor layer outboard of and between said gate electrodes, depositing a roughly aligned mask upon said gate electrodes for blocking said inter-gate distance, and implanting heavily doped source and drain regions in said semiconductor layer in those regions outboard of said gate electrodes.
Claim 2
Dependent Claim
131 words
A process for forming a high voltage thin film transistor comprising the steps of depositing an intrinsic non-single crystal semiconductor layer upon a dielectric substrate, depositing a gate dielectric layer over said intrinsic semiconductor layer, depositing a conductive layer over said gate dielectric layer, patterning said conductive layer with a single mask to form a pair of gate electrodes with a precise distance therebetween, implanting lightly doped regions in said semiconductor layer, using said gate electrodes as an implantation mask, so as to dope those regions of said semiconductor layer outboard of and between said gate electrodes, depositing a roughly aligned mask upon said gate electrodes for blocking said inter-gate distance, and implanting heavily doped source and drain regions in said semiconductor layer in those regions outboard of said gate electrodes.
Claim 3
Dependent Claim
133 words
A process for forming a high voltage thin film transistor comprising the steps of patterning a pair of spaced gate electrodes upon a substrate with a single mask, sequentially depositing a gate dielectric layer, an intrinsic non-single crystal semiconductor layer, and a passivation layer on said substrate, over said gates, forming a pair of masking members upon said semiconductor layer in alignment with said gate electrodes, depositing a rough mask upon and between said pair of masking members, etching said passivation layer outboard of and in alignment with said pair of masking members, depositing a heavily doped non-single crystal semiconductor layer, and lifting off said pair of masking members and said rough mask along with the portion of said heavily doped non-single crystal semiconductor layer overlying said masking members and said rough mask.
Claim 4
Dependent Claim
133 words
A process for forming a high voltage thin film transistor comprising the steps of patterning a pair of spaced gate electrodes upon a substrate with a single mask, sequentially depositing a gate dielectric layer, an intrinsic non-single crystal semiconductor layer, and a passivation layer on said substrate, over said gates, forming a pair of masking members upon said semiconductor layer in alignment with said gate electrodes, depositing a rough mask upon and between said pair of masking members, etching said passivation layer outboard of and in alignment with said pair of masking members, depositing a heavily doped non-single crystal semiconductor layer, and lifting off said pair of masking members and said rough mask along with the portion of said heavily doped non-single crystal semiconductor layer overlying said masking members and said rough mask.
Claim 5
Dependent Claim
44 words
The process for forming a high voltage thin film transistor as defined in claim 2 characterized in that said substrate is transparent and said step of forming a pair of masking members comprises exposing a photoresist layer, overlying said passivation layer, through said substrate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-07-30 | 1994-01-29 | 1994-07-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-07-30 | 1998-01-29 | 1998-07-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-07-30 | 2002-01-29 | 2002-07-31 | $7700.00 | Window Closed / Lapsed |