US4729966A
Expired / Lapsed
US
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Process for manufacturing a Schottky FET device using metal sidewalls as gates
Assignee: Toshiba Corp
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Filing: 1986-03-26
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Granted: 1988-03-08
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Expires: 2006-03-26
Abstract
Abstract A first insulative film is formed with predetermined height and thickness in a loop shape on the surface of the Schottky-junction semiconductor substrate. A gate electrode metal film is formed with a predetermined height and thickness in a loop shape on the surface of the substrate along the inner surface of the first insulative film. A second insulative film is formed with a predetermined height and thickness in a loop shape on the surface of the substrate along the inner surface of the metal film. A channel consisting of a low concentration impurity layer, is formed in a loop shape inside the substrate directly under the metal film and the first and second insulative films. The source region consists of a high-concentration impurity layer formed such that it surrounds the channel positioned inside the substrate on the outside of the first insulative film. The drain region consists of a high-concentration impurity layer, which is formed such that it is surrounded by the channel positioned inside the substrate on the inside of the second insulative film.
Inventors
- 👤 Yutaka Koshino
- 👤 Tatsuo Akiyama
- 👤 Shunichi Hiraki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 15:38
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/061; H10D30/0612; H10D30/0616; H10D64/00; H10D64/01; H10D64/012; H10D64/0124; H10D64/0125; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01326; H10D64/0133
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
236 words
A process for manufacturing a Schottky FET device, comprising: a first step of forming an island-shaped insulative film portion on a surface of a Schottky-junction semiconductor substrate, which has a low-concentration impurity layer on the surface, with the periphery of the insulative film substantially vertical to the substrate surface; a second step of forming a gate electrode metal film in a loop shape and with a predetermined thickness on the outer periphery of said island-shaped insulative film portion; a third step of forming a first insulative film in a loop shape and with a predetermined thickness on the periphery of said loop-shaped gate electrode metal film; a fourth step of forming a second insulative film in a loop shape and with a predetermined thickness of the inner peripheral surface of said loop-shaped gate electrode metal film by removing the center portion of said island-shaped insulation film portion; and a fifth step of forming source and drain regions, which consist of high-concentration impurity layers, inside said substrate on the outside of said first insulative film and on the inside of said second insulative film by driving a high-concentration of impurities into the surface of said substrate other than on said loop-shaped gate electrode metal film and said first and second insulative films, and at the same time forming a channel of the remainder of said low-concentration impurity layer inside said substrate between said source and drain regions.
Claim 2
Dependent Claim
236 words
A process for manufacturing a Schottky FET device, comprising: a first step of forming an island-shaped insulative film portion on a surface of a Schottky-junction semiconductor substrate, which has a low-concentration impurity layer on the surface, with the periphery of the insulative film substantially vertical to the substrate surface; a second step of forming a gate electrode metal film in a loop shape and with a predetermined thickness on the outer periphery of said island-shaped insulative film portion; a third step of forming a first insulative film in a loop shape and with a predetermined thickness on the periphery of said loop-shaped gate electrode metal film; a fourth step of forming a second insulative film in a loop shape and with a predetermined thickness of the inner peripheral surface of said loop-shaped gate electrode metal film by removing the center portion of said island-shaped insulation film portion; and a fifth step of forming source and drain regions, which consist of high-concentration impurity layers, inside said substrate on the outside of said first insulative film and on the inside of said second insulative film by driving a high-concentration of impurities into the surface of said substrate other than on said loop-shaped gate electrode metal film and said first and second insulative films, and at the same time forming a channel of the remainder of said low-concentration impurity layer inside said substrate between said source and drain regions.
Claim 3
Dependent Claim
28 words
A process for manufacturing a Schottky FET device according to claim 1, wherein in said first step said island-shaped insulative film portion is formed using reactive ion etching.
Claim 4
Dependent Claim
36 words
A process for manufacturing a Schottky FET device according to claim 1, wherein in said second step said loop-shaped gate electrode metal film of a predetermined thickness is formed using low-pressure CVD and reactive ion etching.
Claim 5
Dependent Claim
35 words
A process for manufacturing a Schottky FET device according to claim 1, wherein in said third step said loop-shaped first insulative film of a predetermined thickness is formed using low-pressure CVD and reactive ion etching.
Claim 6
Dependent Claim
32 words
A process for manufacturing a Schottky FET device according to claim 1, wherein in said fourth step said loop-shaped second insulative film of a predetermined thickness is formed using reactive ion etching.
Claim 7
Dependent Claim
48 words
A process for manufacturing a Schottky device according to claim 1, wherein said process further comprises a sixth step of depositing ohmic electrode films on said source and drain regions, and also on top end surfaces of said first and second insulative films and gate electrode metal film.
References Cited (Backward Citations)
US3969745A
Cited
US4194935A
Cited
US4322883A
Cited
US4608589A
Cited
US4425379A
Cited
US4389768A
Cited
US4409608A
Cited
US4498093A
Cited
US4455738A
Cited
US4489146A
Cited
US4521952A
Cited
US4532532A
Cited
US4566941A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-03-08 | 1991-09-07 | 1992-03-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-03-08 | 1995-09-07 | 1996-03-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-03-08 | 1999-09-07 | 2000-03-08 | $7700.00 | Window Closed / Lapsed |