US4246044A
Expired / Lapsed
US
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Method for fabricating semi-conductor devices
Assignee: Toshiba Corp
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Filing: 1979-07-05
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Granted: 1981-01-20
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Expires: 1999-07-05
Abstract
Abstract A process for fabricating semi-conductor devices, such as depletion mode MOS transistors, including the process of doping impurities in to the semi-conductor substrate by using a newly provided oxide layer as a doping mask, and thereafter providing a gate oxide layer. A desired gate threshold voltage is thereby reliably obtained.
Inventors
- 👤 Toshinobu Yanase
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 06:42
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0163; H10D84/02; H10D84/03; H10D84/038; H10P; H10P76/00; H10P76/40
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
197 words
A method for fabricating semiconductor devices, comprising the steps of: forming a first oxide layer on a semiconductor substrate of one conductivity type; forming a silicon nitride layer pattern on the first oxide layer; thermally oxidizing the substrate to form a field oxide layer by using said silicon nitride layer as a mask; removing said silicon nitride layer and said first oxide layer underneath said silicon nitride layer to reveal a portion of said substrate; forming a second oxide layer in the revealed portion by thermal oxidation; etching off a part of the second oxide layer to form a window for impurities doping; doping selected impurities through the window by using ion implantation to form a channel region; removing the second oxide layer and newly forming a third oxide layer on the revealed portion of said substrate by thermal oxidation; forming a gate electrode on the third oxide layer; and forming a source region and a drain region of opposite conductivity type adjoining the channel region in the substrate; wherein the third oxide layer which serves as a gate oxide layer, the gate electrode, the source region and the drain region constitute a depletion mode MOS transistor.
Claim 2
Independent Claim
197 words
A method for fabricating semiconductor devices, comprising the steps of: forming a first oxide layer on a semiconductor substrate of one conductivity type; forming a silicon nitride layer pattern on the first oxide layer; thermally oxidizing the substrate to form a field oxide layer by using said silicon nitride layer as a mask; removing said silicon nitride layer and said first oxide layer underneath said silicon nitride layer to reveal a portion of said substrate; forming a second oxide layer in the revealed portion by thermal oxidation; etching off a part of the second oxide layer to form a window for impurities doping; doping selected impurities through the window by using ion implantation to form a channel region; removing the second oxide layer and newly forming a third oxide layer on the revealed portion of said substrate by thermal oxidation; forming a gate electrode on the third oxide layer; and forming a source region and a drain region of opposite conductivity type adjoining the channel region in the substrate; wherein the third oxide layer which serves as a gate oxide layer, the gate electrode, the source region and the drain region constitute a depletion mode MOS transistor.
Claim 3
Dependent Claim
25 words
A method for fabricating semiconductor devices according to claim 1, wherein said selected impurities are of a type different from the impurities of the substrate.
Claim 4
Dependent Claim
25 words
A method for fabricating semiconductor devices according to claim 2, wherein said selected impurities are of a type opposite from the impurities of the substrate.
Claim 5
Dependent Claim
17 words
A method for fabricating semiconductor devices according to claim 1, wherein said selected impurities are arsenic ions.
Claim 6
Dependent Claim
21 words
A method for fabricating semiconductor devices according to claim 4, wherein said second oxide layer thickness is more than 170 A.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-01-20 | 1984-07-21 | 1985-01-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-01-20 | 1988-07-21 | 1989-01-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-01-20 | 1992-07-21 | 1993-01-20 | $7700.00 | Window Closed / Lapsed |