US4466175A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Manufacture of vertical insulated gate field effect transistors
Assignee: US Philips Corp
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Filing: 1982-06-10
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Granted: 1984-08-21
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Expires: 2002-06-10
Abstract
Abstract A vertical insulated gate field effect transistor is made by providing a polycrystalline semiconductor layer on an insulating layer at a surface of an n-type semiconductor body, and thereafter forming gates of the IGFET by laterally diffusing a p-type impurity into the polycrystalline semiconductor layer below two opposite edges of a masking layer. A p-type zone and an n-type source zone are then formed at the surface of the semiconductor body by introducing the relevant impurities in the presence of the masking layer, and then by laterally diffusing these impurities below the gate with the p-type impurities for the p-type zone diffusing laterally farther beneath the gate than the n-type impurities of the source zone. The lateral extent of the source zone, the p-type zone, and the gates can all be predetermined in relation to the same edge of the masking layer which enables improved gate-channel alignment, and so minimizes Miller capacitance of the IGFET.
Inventors
- 👤 David J. Coe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 11:52
CPC Classifications
H; H10; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/66; H10D30/01; H10D30/021; H10D30/028; H10D30/0291; H10D30/662; H10D62/00; H10D62/10; H10D62/17; H10D62/393; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/518; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/021; H10W10/061; H10W10/10; H10W10/13; H10W10/181; H10W10/20; H10D62/13; H10D62/149; H10D62/151; H10D62/156; H10D62/157; H10D64/519
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
328 words
A method of manufacturing an insulated gate field effect transistor including a semiconductor body having source and drain zones respectively adjoining opposite major surfaces of said body comprising the steps of providing a semiconductor body of a first conductivity type with a first insulating layer at portions of a first major surface of said semiconductor body, forming regions of a second conductivity type in said first major surface at portions free of said first insulating layer, removing said first insulating layer and forming a second insulating layer on said first major surface, forming a polycrystalline semiconductor layer on said second insulating layer, forming a masking layer on said polycrystalline layer between said regions of said second conductivity type, removing unmasked portions of said polycrystalline layer, forming gates of the transistor at masked portions of said polycrystalline layer by laterally diffusing a doping element of said second conductivity type into said polycrystalline layer beneath two opposite edges of said masking layer to a predetermined distance, wherein said polycrystalline layer initially has a relatively high resistivity and said gates include pairs of relatively low resistivity conductive strips portions of said laterally diffused portions of said polycrystalline layer, introducing into said semiconductor body impurities of said first conductivity type to form source zones and impurities of said second conductivity type to form zones of said second conductivity type at least partially below said gates, said impurities of said second conductivity type being introduced in the presence of said masking layer, and said zones of said second conductivity type overlying said regions of second conductivity type, said zones having a lower doping then said regions, removing said masking layer and said polycrystalline layer free of said gates, forming an insulating layer over said gates, forming a first electrically conductive layer in contact with said source zones, and forming a second electrically conductive layer at a second major surface of said semiconductor body in contact with a drain zone of said semiconductor body.
Claim 2
Independent Claim
328 words
A method of manufacturing an insulated gate field effect transistor including a semiconductor body having source and drain zones respectively adjoining opposite major surfaces of said body comprising the steps of providing a semiconductor body of a first conductivity type with a first insulating layer at portions of a first major surface of said semiconductor body, forming regions of a second conductivity type in said first major surface at portions free of said first insulating layer, removing said first insulating layer and forming a second insulating layer on said first major surface, forming a polycrystalline semiconductor layer on said second insulating layer, forming a masking layer on said polycrystalline layer between said regions of said second conductivity type, removing unmasked portions of said polycrystalline layer, forming gates of the transistor at masked portions of said polycrystalline layer by laterally diffusing a doping element of said second conductivity type into said polycrystalline layer beneath two opposite edges of said masking layer to a predetermined distance, wherein said polycrystalline layer initially has a relatively high resistivity and said gates include pairs of relatively low resistivity conductive strips portions of said laterally diffused portions of said polycrystalline layer, introducing into said semiconductor body impurities of said first conductivity type to form source zones and impurities of said second conductivity type to form zones of said second conductivity type at least partially below said gates, said impurities of said second conductivity type being introduced in the presence of said masking layer, and said zones of said second conductivity type overlying said regions of second conductivity type, said zones having a lower doping then said regions, removing said masking layer and said polycrystalline layer free of said gates, forming an insulating layer over said gates, forming a first electrically conductive layer in contact with said source zones, and forming a second electrically conductive layer at a second major surface of said semiconductor body in contact with a drain zone of said semiconductor body.
Claim 3
Dependent Claim
46 words
A method according to claim 1, wherein an impurity characteristic of said first conductivity type is introduced into said semiconductor body at said first major surface between said zones of said second conductivity type, said first conductivity type impurity being at areas free of said gates.
Claim 4
Dependent Claim
18 words
A method according to claim 2, wherein said source zones are formed prior to removing said masking layer.
Claim 5
Dependent Claim
46 words
A method according to claim 3, wherein said zones of said second conductivity type extend below said gates from said two opposite edges to an extent constituting channels of the transistor with the edges of said source zones, said channels being precisely defined below said gates.
Claim 6
Dependent Claim
16 words
A method according to claim 4, wherein said gates have gate lengths greater than said channels.
Claim 7
Dependent Claim
46 words
A method according to claim 4, wherein said zones of said second conductivity type extend beyond said gates, and said first conductivity type impurity characteristic at areas free of said gates is sufficiently highly doped so that said channels terminate directly below edges of said gates.
Claim 8
Dependent Claim
46 words
A method according to claim 2, wherein said zones of said second conductivity type extend below said gates from said two opposite edges to an extent constituting channels of the transistor with the edges of said source zones, said channels being precisely defined below said gates.
Claim 9
Dependent Claim
16 words
A method according to claim 7, wherein said gates have gate lengths greater than said channels.
Claim 10
Dependent Claim
46 words
A method according to claim 7, wherein said zones of said second conductivity type extend beyond said gates, and said first conductivity type impurity characteristic at areas free of said gates is sufficiently highly doped so that said channels terminate directly below edges of said gates.
Claim 11
Dependent Claim
20 words
A method according to claim 1, wherein said first electrically conductive layer extends on said insulating layer over said gates.
Claim 12
Dependent Claim
20 words
A method according to claim 1, wherein a relatively low resistivity polycrystalline bar is formed to electrically connect said gates.
Claim 13
Dependent Claim
32 words
A method according to claim 1, wherein said drain zone is formed of a more highly doped region of said first conductivity type at said second major surface of said semiconductor body.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-08-21 | 1988-02-20 | 1988-08-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-08-21 | 1992-02-20 | 1992-08-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-08-21 | 1996-02-20 | 1996-08-21 | $7700.00 | Window Closed / Lapsed |