Patent US1818095A successfully refreshed from Google Patents.
US4914740A
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US
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Charge amplifying trench memory cell
Assignee: International Business Corp
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Filing: 1988-03-07
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Granted: 1990-04-03
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Expires: 2008-03-07
Abstract
Abstract A charge amplifying memory cell and its memory of making based on trench technology. A trench is formed which reaches through an n-type well region to a p + -type substrate. A triple layer is formed on two sidewalls of the trench consisting of two capacitive insulating layers and a intermediate p + polysilicon layer. The trench is then at least partially filled with a conductor, such as polysilicon, facing the triple layer. Thereby, the intermediate polysilicon layer acts as a charge storage node with capacitance to both the substrate and the polysilicon filling the trench. The insulating layer facing the well is opened with a contact hole near its top so that a p + transistor drain is formed in the adjacent well by diffusion from the polysilicon through the contact hole. A p + transistor source is doped into the well with a gate region between it and the drain to provide a write transistor. A p+ region is also formed adjacent a sidewall of the trench other than the one containing the contact hole so that a read transistor is vertically formed in the n-type well between it and the substrate. The intermediate p + polysilicon layer acts as the electrode of this read transistor, whereby stored charge is amplified by the read transistor.
Inventors
- 👤 Donald M. Kenney
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 20:01
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/038; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/405
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
331 words
A gain memory cell device, comprising: a lower region of a high doping concentration of a first conductivity type; a first surface region of a low doping concentration of a second conductivity type formed over said lower region; a trench having a bottom and substantially vertical sidewalls, formed into said first surface region, and extending downward to at least contact said lower region; a nodal layer formed on at least one sidewall of said trench and comprising a first insulating layer facing said first surface region, a first conductive layer facing said first insulating layer and a second insulating layer facing said first conductive layer; a second conductive layer formed in said trench whereby a signal capacitance is formed between said second conductive layer and said first conductive layer; a second surface region of a high doping concentration of said first conductivity type formed in a surface region of said first surface region adjacent said first insulating layer and electrically connected to said first conductive layer; a third surface region of a high doping concentration of said first conductivity type formed in a surface region of said first surface region adjacent said first insulating layer and separated from said second surface region, said third surface region being electrically isolated from said first conductive layer, with said lower region, third surface region and first conductive layer collectively forming a transistor with one of said lower region and third surface region forming a source, the other of said lower region and third surface region forming a drain, and said first conductive layer forming a gate electrode; a fourth surface region of a high doping concentration of said first conductivity type formed in a surface region of said first surface region separated from said first conductive layer by said second surface region and by another portion of said first surface region; a gate electrode formed over said first surface region in an area of said another portion between said second and fourth surface regions.
Claim 2
Dependent Claim
331 words
A gain memory cell device, comprising: a lower region of a high doping concentration of a first conductivity type; a first surface region of a low doping concentration of a second conductivity type formed over said lower region; a trench having a bottom and substantially vertical sidewalls, formed into said first surface region, and extending downward to at least contact said lower region; a nodal layer formed on at least one sidewall of said trench and comprising a first insulating layer facing said first surface region, a first conductive layer facing said first insulating layer and a second insulating layer facing said first conductive layer; a second conductive layer formed in said trench whereby a signal capacitance is formed between said second conductive layer and said first conductive layer; a second surface region of a high doping concentration of said first conductivity type formed in a surface region of said first surface region adjacent said first insulating layer and electrically connected to said first conductive layer; a third surface region of a high doping concentration of said first conductivity type formed in a surface region of said first surface region adjacent said first insulating layer and separated from said second surface region, said third surface region being electrically isolated from said first conductive layer, with said lower region, third surface region and first conductive layer collectively forming a transistor with one of said lower region and third surface region forming a source, the other of said lower region and third surface region forming a drain, and said first conductive layer forming a gate electrode; a fourth surface region of a high doping concentration of said first conductivity type formed in a surface region of said first surface region separated from said first conductive layer by said second surface region and by another portion of said first surface region; a gate electrode formed over said first surface region in an area of said another portion between said second and fourth surface regions.
Claim 3
Dependent Claim
24 words
A gain memory cell device as recited in claim 1, wherein said third and fourth surface regions are on opposite sides of said trench.
Claim 4
Dependent Claim
21 words
A gain memory cell is recited in claim 2, further comprising a metal interconnect connecting said third and fourth surface regions.
Claim 5
Dependent Claim
26 words
A gain memory cell device as recited in claim 1, wherein said third and fourth surface regions are continuous on a same side of said trench.
Claim 6
Dependent Claim
60 words
A gain memory cell as recited in claim 4, wherein said trench has a first portion and a second portion orthogonal thereto and said nodal layer is formed on sidewalls of both said first and second portions, said second surface region being formed adjacent said first portion and said third and fourth surface regions being formed adjacent said second portion.
Claim 7
Dependent Claim
47 words
A gain memory cell array as recited in claim 5, wherein two said second conductive layers are formed on opposing lateral sides of said first portion of said trench and two said nodal layers are formed on opposing lateral sides of said second portion of said trench.
Claim 8
Dependent Claim
25 words
A gain memory cell as recited in claim 2, wherein said doping concentration of said first surface region increases away from an upper surface thereof.
Claim 9
Dependent Claim
231 words
A two-device dynamic RAM cell disposed on a portion of a silicon substrate of a first conductivity type having a well region of a second conductivity type formed therein, comprising: a horizontal first FET device formed on a surface of the substrate, said first FET device having source and drain regions defined by first and second diffusion regions, respectively, of said first conductivity type, and having a gate electrode defined by a conductive structure overlying a portion of the substrate between said first and second diffusion regions; a storage capacitor charge plate formed within a trench etched into a portion of said surface of the substrate adjacent to said first diffusion region of said first FET device and extending through said well to the substrate, said trench having sidewalls and a bottom that are coated by at least a first dielectric layer and at least a first conductive layer overlying said first dielectric layer, said first conductive layer being electrically coupled to said first diffusion region; and a vertical second FET device formed on one of said sidewalls of said trench, said second FET device having a source region defined by a third diffusion region of said first conductivity type abutting said trench and electrically isolated from said first conductive layer, a drain region defined by the substrate and a gate electrode defined by said first conductive layer within said trench.
Claim 10
Dependent Claim
231 words
A two-device dynamic RAM cell disposed on a portion of a silicon substrate of a first conductivity type having a well region of a second conductivity type formed therein, comprising: a horizontal first FET device formed on a surface of the substrate, said first FET device having source and drain regions defined by first and second diffusion regions, respectively, of said first conductivity type, and having a gate electrode defined by a conductive structure overlying a portion of the substrate between said first and second diffusion regions; a storage capacitor charge plate formed within a trench etched into a portion of said surface of the substrate adjacent to said first diffusion region of said first FET device and extending through said well to the substrate, said trench having sidewalls and a bottom that are coated by at least a first dielectric layer and at least a first conductive layer overlying said first dielectric layer, said first conductive layer being electrically coupled to said first diffusion region; and a vertical second FET device formed on one of said sidewalls of said trench, said second FET device having a source region defined by a third diffusion region of said first conductivity type abutting said trench and electrically isolated from said first conductive layer, a drain region defined by the substrate and a gate electrode defined by said first conductive layer within said trench.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-04-02 | 1993-10-02 | 1994-04-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-04-02 | 1997-10-02 | 1998-04-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-04-02 | 2001-10-02 | 2002-04-03 | $7700.00 | Window Closed / Lapsed |