Random access MOS memory cell using double level polysilicon

Claim 1

A dynamic one-transistor memory cell having a field-effect transistor and a capacitor, comprising: an impurity-doped capacitor region and an impurity-doped transistor region in a face of a semiconductor body, the capacitor region and the transistor region each being doped with impurity of type opposite that of the semiconductor body beneath such regions, the transistor region being spaced from the capacitor region along the face by a channel region, a first conductor layer on said face over the capacitor region but insulted therefrom by a first insulator, the first conductor layer extending beyond the capacitor region along the face for connection to an electrical potential level, a second conductor layer on said face over said transistor region and said channel region but insulated therefrom by a second insulator, providing a transistor gate, the second conductor layer also extending over the first conductor layer but insulated therefrom by a third insulator, said first and second conductor layers being wholly insulated from one another, from said face of the semiconductor body, and from any other conductor layers, in the vicinity of said cell, by said first, second and third insulators.