US3701980A
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High density four-transistor mos content addressed memory
Assignee: General Electric Co
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Filing: 1970-08-03
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Granted: 1972-10-31
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Expires: 1990-08-03
Abstract
Abstract A content addressed memory cell containing the minimum number of access lines and the minimum number of semiconductor devices is disclosed. In this cell, each intersection of the DATA, DATA, WORD, and FLAG lines contains a single transistor; preferably a metal-oxide semiconductor, field-effect transistor. By appropriate selection of these lines as inputs and outputs to the cell, the functions of writing, reading, searching, searching with mask, and refreshing are obtained.
Inventors
- 👤 Joseph L Mundy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 06:21
CPC Classifications
G; G11; G11C; G11C15/00; G11C15/04; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1064; G11C11/00; G11C11/21; G11C11/24; H; H03; H03M; H03M13/00; H03M13/03
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
142 words
A memory cell comprising: two pairs of MOS transistors, each pair capable of acting independently of the other; four signal lines; a first of said pairs comprising first and second MOS transistors having the drains thereof connected together, the source of the first transistor connected to the gate of the second transistor, and the drains of said transistors, the gate of the first transistor and the source of the second transistor connected to three of said four signal lines; the other of said pairs comprising third and fourth MOS transistors having the drains thereof connected together, the source of the third transistor connected to the gate of the fourth transistor and the drains of said third and fourth transistors, the gate of said third transistor and the source of said fourth transistor connected to a different three of said four signal lines.
Claim 2
Dependent Claim
142 words
A memory cell comprising: two pairs of MOS transistors, each pair capable of acting independently of the other; four signal lines; a first of said pairs comprising first and second MOS transistors having the drains thereof connected together, the source of the first transistor connected to the gate of the second transistor, and the drains of said transistors, the gate of the first transistor and the source of the second transistor connected to three of said four signal lines; the other of said pairs comprising third and fourth MOS transistors having the drains thereof connected together, the source of the third transistor connected to the gate of the fourth transistor and the drains of said third and fourth transistors, the gate of said third transistor and the source of said fourth transistor connected to a different three of said four signal lines.
Claim 3
Dependent Claim
46 words
A memory cell as set forth in claim 1 wherein said four signal lines comprise DATA, DATA, WORD, and FLAG lines and wherein the first transistor pair interconnects said DATA, WORD, and FLAG lines and the second transistor pair interconnects said DATA, WORD, and FLAG lines.
Claim 4
Dependent Claim
62 words
A memory cell as set forth in claim 2 wherein: the source electrode of said one transistor is coupled to said FLAG line; the gate electrode of said other transistor is coupled to said WORD line; and the drain electrodes of both transistors are coupled in a first pair, to the DATA line and, in the second pair, to the DATA line.
Claim 5
Dependent Claim
29 words
A memory cell as set forth in claim 3 further comprising: a fifth transistor coupling to said FLAG line the source electrodes of said one transistors in each pair.
Claim 6
Dependent Claim
22 words
A memory cell as set forth in claim 2 further comprising: a fifth transistor coupling said transistor pairs to said FLAG line.
Claim 7
Dependent Claim
140 words
A computer memory containing a plurality of memory cells arranged in a matrix array wherein each memory cell comprises: four signal lines; two pairs of MOS transistors, each pair interconnecting different sets of three of said signal lines; and wherein each pair comprises first and second MOS transistors having the gate of said second transistor connected to the source of said first transistor and the drain of said first and second transistors connected together, the gate of said second transistor and the source of said first transistor forming a storage node, said first transistor acting as a gate for blocking or passing signals from said signal lines to said storage node and said second transistor blocking or passing signals to said signal lines from said storage node in accordance with the information stored on the storage node of each set.
Claim 8
Dependent Claim
140 words
A computer memory containing a plurality of memory cells arranged in a matrix array wherein each memory cell comprises: four signal lines; two pairs of MOS transistors, each pair interconnecting different sets of three of said signal lines; and wherein each pair comprises first and second MOS transistors having the gate of said second transistor connected to the source of said first transistor and the drain of said first and second transistors connected together, the gate of said second transistor and the source of said first transistor forming a storage node, said first transistor acting as a gate for blocking or passing signals from said signal lines to said storage node and said second transistor blocking or passing signals to said signal lines from said storage node in accordance with the information stored on the storage node of each set.
Claim 9
Dependent Claim
32 words
A computer memory as set forth in claim 6 further comprising: a fifth MOS transistor for coupling both transistor sets to a signal line common to both sets of three signal lines.
Claim 10
Dependent Claim
70 words
A read only-search only memory containing a plurality of memory cells arranged in a matrix array containing a FLAG line and parallel DATA and DATA lines intersecting said FLAG line, each memory cell comprising a pair of fixed impedance means, each in either a low or a high impedance condition, depending upon the information to be permanently stored, and coupling said FLAG line to said DATA and DATA lines, respectively.
Claim 11
Dependent Claim
70 words
A read only-search only memory containing a plurality of memory cells arranged in a matrix array containing a FLAG line and parallel DATA and DATA lines intersecting said FLAG line, each memory cell comprising a pair of fixed impedance means, each in either a low or a high impedance condition, depending upon the information to be permanently stored, and coupling said FLAG line to said DATA and DATA lines, respectively.
Claim 12
Dependent Claim
23 words
A read only-search only memory as set forth in claim 8 wherein said low or high impedances comprise short or open circuits, respectively.
Claim 13
Dependent Claim
40 words
A read only-search only memory as set forth in claim 8 further comprising transistor means for coupling both of said fixed impedance means to said FLAG line, whereby the contents of the memory cell is isolated from the FLAG line.
Claim 14
Dependent Claim
94 words
A computer memory containing a plurality of memory cells arranged in a matrix array, said plurality of memory cells divisible into two groups and comprising: erasable and non-erasable memory cells; each erasable memory cell comprising four sIgnal lines and four MOS transistors; said transistors being grouped into two pairs, each pair interconnecting a different set of three of said four signal lines; each non-erasable memory cell comprising a pair of fixed impedances, each in either a low or high impedance condition and coupling said signal lines into two different sets of two lines each.
Claim 15
Dependent Claim
94 words
A computer memory containing a plurality of memory cells arranged in a matrix array, said plurality of memory cells divisible into two groups and comprising: erasable and non-erasable memory cells; each erasable memory cell comprising four sIgnal lines and four MOS transistors; said transistors being grouped into two pairs, each pair interconnecting a different set of three of said four signal lines; each non-erasable memory cell comprising a pair of fixed impedances, each in either a low or high impedance condition and coupling said signal lines into two different sets of two lines each.
Claim 16
Dependent Claim
21 words
A computer memory as set forth in claim 11 wherein said plurality of memory cells are fabricated on a single substrate.
Claim 17
Dependent Claim
70 words
A computer memory as set forth in claim 11 wherein said four signal lines comprise DATA, DATA, WORD, and FLAG lines; said MOS transistor pairs comprise a first MOS transistor acting as a gate for blocking or passing signals from said signal lines and a second MOS transistor for blocking or passing signals to said signal lines in accordance with the charge stored on the nodal capacitance of said pair.
Claim 18
Dependent Claim
29 words
A computer memory as set forth in claim 13 wherein said MOS transistor pairs interconnect said DATA, WORD, and FLAG lines and said DATA, WORD, and FLAG lines, respectively.
Claim 19
Dependent Claim
26 words
A computer memory as set forth in claim 14 and further comprising: a fifth transistor coupling both of said MOS transistor pairs to said FLAG line.
Claim 20
Dependent Claim
56 words
A computer memory as set forth in claim 13 wherein said non-erasable memory cell comprises: DATA, DATA, and FLAG signal lines; a pair of fixed impedance means, each in either a high or a low impedance state, depending upon the information to be permanently stored, coupling said FLAG line to said DATA and DATA lines, respectively.
Claim 21
Dependent Claim
26 words
A computer memory as set forth in claim 16 and further comprising: a transistor for coupling both of said fixed impedance means to said FLAG line.
Claim 22
Dependent Claim
29 words
A computer memory as set forth in claim 16 wherein said MOS transistor pairs interconnect said DATA, WORD, and FLAG lines and said DATA, WORD, and FLAG lines, respectively.
Claim 23
Dependent Claim
32 words
A computer memory as set forth in claim 18 and further comprising: a fifth transistor in said erasable memory cell for coupling both of said MOS transistor pairs to said FLAG line.
Claim 24
Dependent Claim
31 words
A computer memory as set forth in claim 19 and further comprising: a transistor in said non-erasable memory cell for coupling both of said fixed impedance means to said FLAG line.
Claim 25
Dependent Claim
32 words
A computer memory as set forth in claim 20 wherein said fifth transistor in said erasable memory cell and said transistor in said non-erasable memory cell are of the field effect type.
Claim 26
Dependent Claim
31 words
A computer memory as set forth in claim 20 wherein said fifth transistor in said erasable memory cell and said transistor in said non-erasable memory cell are of the bi-polar type.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-10-31 | 1976-05-01 | 1976-10-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-10-31 | 1980-05-01 | 1980-10-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-10-31 | 1984-05-01 | 1984-10-31 | $7700.00 | Window Closed / Lapsed |