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Monolithic temperature compensated voltage-reference diode and method for its manufacture

Assignee: Semiconductor Components Industries LLC
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Filing: 1989-07-03
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Granted: 1989-12-12
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Expires: 2009-07-03
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Abstract

Abstract An improved monolithic, temperature compensated voltage- reference diode is realized by creating a tub of epitaxial semiconductor material in a substrate of opposite conductivity type and creating a voltage reference junction at a surface of the tub. The junction between the tub and the substrate forms the forward-biased, temperature compensating junction of the device. The dopant concentration is varied during growth of the epitaxial material to provide a relatively low resistivity at the voltage-reference junction and a higher resistivity at the temperature compensating junction. The method described offers significant improvement over prior methods of manufacturing such devices in the area of cost and reliability.

Inventors

  • 👤 Bernard W. Boland
  • 👤 William E. Gandy, Jr.
  • 👤 Kevin B Jackson

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 08:39
CPC Classifications
H; H10; H10D; H10D8/00; H10D8/20; H10D8/25; Y; Y10; Y10S; Y10S148/00; Y10S148/174; Y10S438/00; Y10S438/983

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 165 words
A method of manufacturing a monolithic, temperature compensated voltage-reference diode in a body of semiconductor material having first and second major faces comprising the steps of: forming a temperature compensation junction between semiconductor material of different conductivity types, said temperature compensation junction intersecting said first major face of said body and defining a portion of said body bounded by said temperature compensation junction and said first major face; providing a region of varying resistivity in said portion of said body and having a first resistivity adjacent said temperature compensation junction and a second resistivity adjacent at least a portion of said first major face and an impurity concentration adjacent said temperature compensation junction on a side of said temperature compensation junction in said portion less than an impurity concentration in said body on the other side of said temperature compensation junction; and forming a voltage reference junction between semiconductor material of different conductivity types near said first major face in said portion of said body.
Claim 2
Independent Claim 165 words
A method of manufacturing a monolithic, temperature compensated voltage-reference diode in a body of semiconductor material having first and second major faces comprising the steps of: forming a temperature compensation junction between semiconductor material of different conductivity types, said temperature compensation junction intersecting said first major face of said body and defining a portion of said body bounded by said temperature compensation junction and said first major face; providing a region of varying resistivity in said portion of said body and having a first resistivity adjacent said temperature compensation junction and a second resistivity adjacent at least a portion of said first major face and an impurity concentration adjacent said temperature compensation junction on a side of said temperature compensation junction in said portion less than an impurity concentration in said body on the other side of said temperature compensation junction; and forming a voltage reference junction between semiconductor material of different conductivity types near said first major face in said portion of said body.
Claim 3
Independent Claim 139 words
A method of menufacturing a temperature compensated voltage reference device in a body of semiconductor material of a first type and having a first major face, comprising the steps of: forming a cavity in said body of semiconductor material at said first major face; forming a layer of epitaxial material on said first major face of said body and filling said cavity, said epitaxial material being of a second conductivity type opposite to that of said body and of varying resistivity in said cavity decreasing outwardly from said body; shaping back said epitaxial material to re-expose said first major face of said body and to leave a tub of said epitaxial material of varying resistivity filling said cavity; and forming a region of said first conductivity type in said tub of epitaxial material, extending to an outward surface thereof.
Claim 4
Independent Claim 139 words
A method of menufacturing a temperature compensated voltage reference device in a body of semiconductor material of a first type and having a first major face, comprising the steps of: forming a cavity in said body of semiconductor material at said first major face; forming a layer of epitaxial material on said first major face of said body and filling said cavity, said epitaxial material being of a second conductivity type opposite to that of said body and of varying resistivity in said cavity decreasing outwardly from said body; shaping back said epitaxial material to re-expose said first major face of said body and to leave a tub of said epitaxial material of varying resistivity filling said cavity; and forming a region of said first conductivity type in said tub of epitaxial material, extending to an outward surface thereof.
Claim 5
Dependent Claim 42 words
A method of manufacturing according to claim 2 wherein said step of forming a layer of epitaxial material further comprises the step of: varying a concentration of a dopant material introduced into said epitaxial material while said epitaxial material is being formed.
Claim 6
Dependent Claim 44 words
The method of manufacturing according to claim 2 further comprising the step of: forming a guard ring of a conductivity type opposite to that of said epitaxial material and surrounding said region, said guard ring having a resistivity higher than that of said region.
Claim 7
Independent Claim 98 words
A method of manufacturing a monolithic, temperature compensated voltage-reference diode in a semiconductor body of a first conductivity type, comprising the steps of: forming a cavity in said semiconductor body, said cavity extending inward from a first major surface of said body; filling said cavity with epitaxial semiconductor material of a second conductivity type opposite said first type, said epitaxial material having a first resistivity adjacent said body and a second, lower, resistivity further from said body; and forming a region of said first conductivity type in said material filling said cavity and extending to a surface thereof.
Claim 8
Independent Claim 98 words
A method of manufacturing a monolithic, temperature compensated voltage-reference diode in a semiconductor body of a first conductivity type, comprising the steps of: forming a cavity in said semiconductor body, said cavity extending inward from a first major surface of said body; filling said cavity with epitaxial semiconductor material of a second conductivity type opposite said first type, said epitaxial material having a first resistivity adjacent said body and a second, lower, resistivity further from said body; and forming a region of said first conductivity type in said material filling said cavity and extending to a surface thereof.
Claim 9
Dependent Claim 35 words
The method according to claim 5 further comprising the step of: forming a guard ring of said first conductivity type surrounding said region, said guard ring having a resistivity higher than that of said region.
Claim 10
Dependent Claim 17 words
The method of claim 5 wherein said region has a third resistivity lower than said first resistivity.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-12-11 1993-06-12 1993-12-12 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-12-11 1997-06-12 1997-12-12 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-12-11 2001-06-12 2001-12-12 $7700.00 Window Closed / Lapsed

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