US4732866A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for producing low noise, high grade constant semiconductor junctions
Assignee: Semiconductor Components Industries LLC
•
Filing: 1984-03-12
•
Granted: 1988-03-22
•
Expires: 2004-03-12
Abstract
Abstract Zener diodes and other semiconductor junctions having very low noise characteristics and improved yield may be obtained by first ion implanting a suitable impurity into a substrate wafer, and then forming the p-n junction using a very rapid thermal activation and annealing process. For p-n junctions formed with boron (11B) implanted into n-type silicon to a peak concentration exceeding 1020 atoms/cm3, the rapid activation process comprises heating from about room temperature to about 1150 DEG C. in 12-30 seconds, and then cooling back below 1000 degrees C. in less than 5 seconds. Noise voltages measured on devices formed using the invented process were typically much lower and more narrowly grouped than on devices of the prior art. Dynamic impedance was also slightly reduced.
Inventors
- 👤 Jerry L. Chruma
- 👤 William E. Gandy, Jr.
- 👤 Tommie R. Huffman
- 👤 Syd R. Wilson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:39
CPC Classifications
H; H10; H10D; H10D8/00; H10D8/20; H10D8/25; H10P; H10P30/00; H10P30/20; H10P30/21; H10D84/00; H10D84/101; H10D84/141; H10D84/148; H10P30/202; H10P30/204; H10P30/28; H10P95/00; H10P95/90
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
85 words
A process for forming low noise semiconductor junctions comprising: providing a semiconductor substrate containing an impurity of a first conductivity type and a first concentration; implanting an impurity of a second type in said substrate to a dose about 1×10 16 ions/cm 2 or larger; and rapidly heating and cooling said substrate without melting to activate an increase the depth of penetration of said implanted impurity without decreasing the slope of the concentration profile of said implanted impruity in said substrate at said first concentration.
Claim 2
Dependent Claim
85 words
A process for forming low noise semiconductor junctions comprising: providing a semiconductor substrate containing an impurity of a first conductivity type and a first concentration; implanting an impurity of a second type in said substrate to a dose about 1×10 16 ions/cm 2 or larger; and rapidly heating and cooling said substrate without melting to activate an increase the depth of penetration of said implanted impurity without decreasing the slope of the concentration profile of said implanted impruity in said substrate at said first concentration.
Claim 3
Dependent Claim
32 words
The process of claim 1 wherein said implanting step comprises implanting said impurity so that the peak of said implanted distribution lies less than 0.3 microns from the surface of said substrate.
Claim 4
Dependent Claim
32 words
The process of claim 14 wherein said rapidly heating and cooling step comprises rapidly heating and cooling said saubstrate so that the total time above 1000° C. is less than 40 seconds.
Claim 5
Dependent Claim
68 words
A process for forming low noise semiconductor junctions comprising: providing a semiconductor substrate containing an impurity of a first conductivity type and a first concentration; implanting an impurity of a second type in said substrate to a dose of 1×10 16 ions/cm 2 or larger; and rapidly heating and cooling said substrate without melting to a temperature exceeding 1000° C. for a time less than about 40 seconds.
Claim 6
Dependent Claim
68 words
A process for forming low noise semiconductor junctions comprising: providing a semiconductor substrate containing an impurity of a first conductivity type and a first concentration; implanting an impurity of a second type in said substrate to a dose of 1×10 16 ions/cm 2 or larger; and rapidly heating and cooling said substrate without melting to a temperature exceeding 1000° C. for a time less than about 40 seconds.
References Cited (Backward Citations)
US3515956A
Cited
US3638300A
Cited
US3634738A
Cited
US3856578A
Cited
US4155777A
Cited
US4030117A
Cited
US4155778A
Cited
US4393575A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-03-22 | 1991-09-21 | 1992-03-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-03-22 | 1995-09-21 | 1996-03-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-03-22 | 1999-09-21 | 2000-03-22 | $7700.00 | Window Closed / Lapsed |