US4155778A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Forming semiconductor devices having ion implanted and diffused regions
Assignee: International Business Machines Corp
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Filing: 1977-12-30
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Granted: 1979-05-22
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Expires: 1997-12-30
Abstract
Abstract A method for making ion implanted resistors in conjunction with transistors and other devices within an integrated circuit semiconductor substrate. The implantation of the resistors is done after a predeposition diffusion of the base region of the transistors but prior to the base drive-in step. The subsequent emitter thermal diffusion, or annealing step in the case of ion implanted emitters, consitutes the annealing step for the ion implanted resistor regions.
Inventors
- 👤 Igor Antipov
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:27
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/21; H10D; H10D84/00; H10D84/01; H10D84/0112; H10D84/02; H10D84/03; H10D84/038; H10D84/101; H10D84/121; H10D84/125; H10D84/60; H10D84/611; H10D84/613; H10D84/615; H10P30/202; H10P30/204; H10P30/28
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
251 words
A method of fabricating an integrated circuit semiconductor device, which includes a semiconductor layer of a first conductivity type in which active devices and resistors are to be formed, comprising the steps of: forming a first masking means over said semiconductor layer, said first masking means having a first predetermined pattern of openings; introducing impurities of a second conductivity type into selected regions of said layer by a predeposition diffusion step to form at least first active device regions, said first masking means protecting the remainder of said layer; forming a second masking means over said first masking means, said second masking means having another predetermined pattern of openings; removing at least a portion of said first masking means exposed by said other openings; implanting ions of a selected conductivity type through said other openings into other selected regions of said layer at a relatively low energy level to form resistor regions, said second masking means protecting the remainder of said layer to prevent ion implantation therethrough; removing said second masking means; oxidizing said layer at high temperature in an oxygen atmosphere, thereby driving-in said predeposited impurities to form first active device regions; introducing impurities of a first conductivity type into a selected area of each of said first active device regions so as to form second active device regions; said impurities of said first conductivity type being introduced by a process which includes diffusion at high temperature so as to cause an annealing of said implanted ions in said resistor.
Claim 2
Independent Claim
251 words
A method of fabricating an integrated circuit semiconductor device, which includes a semiconductor layer of a first conductivity type in which active devices and resistors are to be formed, comprising the steps of: forming a first masking means over said semiconductor layer, said first masking means having a first predetermined pattern of openings; introducing impurities of a second conductivity type into selected regions of said layer by a predeposition diffusion step to form at least first active device regions, said first masking means protecting the remainder of said layer; forming a second masking means over said first masking means, said second masking means having another predetermined pattern of openings; removing at least a portion of said first masking means exposed by said other openings; implanting ions of a selected conductivity type through said other openings into other selected regions of said layer at a relatively low energy level to form resistor regions, said second masking means protecting the remainder of said layer to prevent ion implantation therethrough; removing said second masking means; oxidizing said layer at high temperature in an oxygen atmosphere, thereby driving-in said predeposited impurities to form first active device regions; introducing impurities of a first conductivity type into a selected area of each of said first active device regions so as to form second active device regions; said impurities of said first conductivity type being introduced by a process which includes diffusion at high temperature so as to cause an annealing of said implanted ions in said resistor.
Claim 3
Dependent Claim
19 words
A method as in claim 1 wherein said impurities of said first conductivity type are introduced by ion implantation.
Claim 4
Dependent Claim
19 words
A method as in claim 1 wherein said impurities of said first conductivity type are introduced by capsule diffusion.
Claim 5
Dependent Claim
33 words
A method as in claim 1 wherein said resistor ions are of said second conductivity type and contact regions for said resistors are formed during the formation of said first active device regions.
Claim 6
Dependent Claim
61 words
A method as in claim 1 wherein said predeposition diffusion comprises the steps of: depositing BBr 3 atop said layer in an oxygen atmosphere for a sufficient time and temperature to cause boron atoms to enter said first active device regions; and removing the residue of said BBr 3 deposition from the surface of said layer prior to said oxidizing step.
Claim 7
Dependent Claim
34 words
A method as in claim 5 wherein said resistor ions are of the same conductivity type as boron and contacts for said resistor are formed during the formation of said first active device regions.
Claim 8
Dependent Claim
20 words
A method as in claim 6 wherein said first and second active device regions are base and emitter regions, respectively.
Claim 9
Dependent Claim
39 words
A method as in claim 1 further comprising the steps of performing a second ion implantation step after said ion implantation step into a set of said other selected regions so as to form resistors having different resistive values.
Claim 10
Dependent Claim
33 words
A method as in claim 1 wherein said resistor ions are of said first conductivity type and contact regions for said resistors are formed during the formation of said second active device regions.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-05-21 | 1982-11-20 | 1983-05-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-05-21 | 1986-11-20 | 1987-05-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-05-21 | 1990-11-20 | 1991-05-22 | $7700.00 | Window Closed / Lapsed |