Punch through reference diode

Claim 2

A punch-through reference diode comprising: a semiconductor body; a first semiconductor region of a first conductivity type which is formed within said semiconductor body; a second semiconductor region of a second conductivity type which is formed within said semiconductor body, said second semiconductor region adjoining said first semiconductor region and defining a first PN-junction with said first semiconductor region; and a third semiconductor region of said first conductivity type which is formed within said semiconductor body, said third semiconductor region adjoining said second semiconductor region and defining a second PN-junction with said second semiconductor region, whereby said second semiconductor region is located between said first PN-junction and said second PN-junction; wherein said second semiconductor region has an impurity concentration distribution in which a concentration of an impurity of said second conductivity type increases from said first PN-junction towards said second PN-junction; said first and second semiconductor regions are provided with a connection for electrically connecting them in order to short said first PN-junction; said first and third semiconductor regions are respectively provided with connections for supplying a voltage so as to reverse-bias said second PN-junction; and a Zener breakdown voltage of said second PN-junction is greater than a punch-through voltage between said first and third semiconductor regions.

Claim 3

A punch-through reference diode according to claim 1, wherein said first and third semiconductor regions are of the P-type, and said second semiconductor region is of the N-type.

Claim 4

A punch-through reference diode according to claim 2, wherein said first semiconductor region consists of a P-type substrate which is heavily doped, and an epitaxial layer which is formed on said substrate and which is lightly doped, and wherein said epitaxial layer adjoins said second semiconductor region so as to form said first PN-junction with said second semiconductor region.

Claim 5

A punch-through reference diode according to claim 3, wherein said second semiconductor region is doped with an impurity selected from the group consisting of antimony and arsenic, while said third semiconductor region is doped with an impurity of boron.

Claim 6

A punch-through reference diode according to claim 1, wherein said semiconductor body comprises: a first semiconductor layer of said first conductivity type having a relatively high impurity concentration ahd having first and second surfaces; and a second semiconductor layer disposed on said second surface of said first semiconductor layer and being comprised of said first, second, and third semiconductor regions, said second semiconductor layer having a first surface contacted with said second surface of said first semiconductor layer and a second surface opposite to said first surface of said second semiconductor layer.

Claim 7

A punch-through reference diode according to claim 1, wherein said semiconductor body has first and second surfaces and is comprised of said first, second, and third semiconductor regions, said first semiconductor region extending to both said first and second surfaces, said second and third semiconductor regions extending to said first surface.

Claim 8

A punch-through reference diode according to claim 5, wherein an electrode is provided in the first surface of said first semiconductor layer, and said connection is comprised of an annular-shaped ring electrode disposed on the second surface of said second semiconductor layer.

Claim 9

A punch-through reference diode according to claim 6, wherein said connection comprises an electrode in contact with said first and second semiconductor regions at the first surface of said semiconductor body.

Claim 10

A punch-through reference diode according to claim 1, wherein the thickness of said second semiconductor region is smaller than the thickness of said first semiconductor region.

Claim 11

A punch-through reference diode according to claim 6, wherein said semiconductor body further comprises a fourth semiconductor region of said first conductivity type and having relatively low impurity concentration, said fourth semiconductor region being buried within said semiconductor body by being disposed between said first and second semiconductor regions.

Claim 12

A punch-through reference diode according to claim 5, further comprising a fourth semiconductor region, of said first conductivity type and having a relatively high impurity concentration, surrounding and adjoining said second semiconductor region and extending from the second surface of said second semiconductor layer to the second surface of said first semiconductor layer.

Claim 13

A punch-through reference diode according to claim 11, further comprising a fifth semiconductor region, of said second conductivity type ahd having a relatively high impurity concentration, extending from said second surface of said second semiconductor layer and being contiguous with said second semiconductor region and said fourth semiconductor region.

Claim 14

A punch-through reference diode according to claim 12, wherein said connection comprises an electrode in ohmic contact, at the second surface of said second semiconductor layer, with said fourth and fifth semiconductor regions.

Claim 15

A punch-through reference diode according to claim 13, further comprising a bump-shaped electrode structure in ohmic contact with said third semiconductor region and extending over and beyond the intersection of said second PN-junction at the second surface of said semiconductor layer.

Claim 16

A punch-through reference diode according to claim 14, wherein said first semiconductor layer and said first, third and fourth semiconductor regions are of the P-type, and said second and fifth semiconductor regions are of the N-type.

Claim 17

A punch-through reference diode according to claim 15, wherein said bump-shaped electrode structure is made of silver.

Claim 18

A punch-through reference diode constructed of a three-layer transistor device, comprising: a semiconductor body; a first semiconductor region of a first conductivity type which is formed within said semiconductor body to form a collector of said transistor; a second semiconductor region of a second conductivity type which is formed within said semiconductor body to form a base of said transistor, said second semiconductor region adjoining said first semiconductor region and defining a base-collector PN-junction with said first semiconductor region; and a third semiconductor region of said first conductivity type which is formed within said semiconductor body to form an emitter of said transistor, said third semiconductor region adjoining said second semiconductor region and defining a base-emitter PN-junction with said second semiconductor region, whereby said second semiconductor region is located between said base-collector PN-junction and said base-emitter PN-junction; wherein said second semiconductor region has an impurity concentration distribution in which the concentration of an impurity of said second conductivity type increases from said base-collector PN-junction towards said base-emitter PN-junction, and said first and second semiconductor regions are provided with a connection for electrically connecting them in order to short said base-collector PN-junction; and means for supplying a voltage to said first and third semiconductor regions to reverse-bias said base-emitter PN-junction to form a depletion layer in said second semiconductor region so that transistor operation of said three-layer transistor device is prevented while a punch-through operation is permitted between said first semiconductor region and said third semiconductor region when a reverse-bias voltage exceeding a predetermined punch-through voltage is applied to the base-emitter PN-junction to extend said depletion layer from said first semiconductor layer to said third semiconductor layer.

Claim 19

A punch-through reference diode constructed of a three-layer transistor device, comprising: a semiconductor body; a first semiconductor region of a first conductivity type which is formed within said semiconductor body to form a collector of said transistor; a second semiconductor region of a second conductivity type which is formed within said semiconductor body to form a base of said transistor, said second semiconductor region adjoining said first semiconductor region and defining a base-collector PN-junction with said first semiconductor region; and a third semiconductor region of said first conductivity type which is formed within said semiconductor body to form an emitter of said transistor, said third semiconductor region adjoining said second semiconductor region and defining a base-emitter PN-junction with said second semiconductor region, whereby said second semiconductor region is located between said base-collector PN-junction and said base-emitter PN-junction; wherein said second semiconductor region has an impurity concentration distribution in which the concentration of an impurity of said second conductivity type increases from said base-collector PN-junction towards said base-emitter PN-junction, and said first and second semiconductor regions are provided with a connection for electrically connecting them in order to short said base-collector PN-junction; and means for supplying a voltage to said first and third semiconductor regions to reverse-bias said base-emitter PN-junction to form a depletion layer in said second semiconductor region so that transistor operation of said three-layer transistor device is prevented while a punch-through operation is permitted between said first semiconductor region and said third semiconductor region when a reverse-bias voltage exceeding a predetermined punch-through voltage is applied to the base-emitter PN-junction to extend said depletion layer from said first semiconductor layer to said third semiconductor layer.

Claim 20

A punch-through reference diode, comprising: a first semiconductor layer of P conductivity type having a relatively high impurity concentration and having first and second surfaces; and a second semiconductor layer disposed on said second surface of said first semiconductor layer, said second semiconductor layer having a first surface contacted with said second surface of said first semiconductor layer and a second surface opposite to said first surface of said second semiconductor layer, said second semiconductor layer comprising: p2 a first semiconductor region of P conductivity type having an impurity concentration less than that of said first semiconductor region being in contact with the second surface of said first semiconductor layer; a second semiconductor region of N conductivity type, said second semiconductor region adjoining said first semiconductor region and defining a first PN-junction with said first semiconductor region; a third semiconductor region of P conductivity type, said third semiconductor region adjoining said second semiconductor region and defining a second PN-junction with said second semiconductor region, whereby said second semiconductor region is located between said first PN-junction and said second PN-junction; a ring-shaped fourth semiconductor region, of P conductivity type and having a relatively high impurity concentration, surrounding and adjoining said second semiconductor region and extending from the second surface of said second semiconductor layer to the second surface of said first semiconductor layer; a ring-shaped fifth semiconductor region, of N conductivity type and having a relatively high impurity concentration, extending from said second surface of said second semiconductor layer and being contiguous with said second semiconductor region and said fourth semiconductor region; a ring-shaped electrode in ohmic contact, at the second surface of said second semiconductor layer, with said fourth and fifth semiconductor regions to short said first PN-junction; a bump-shaped electrode structure in ohmic contact with said third semiconductor region and extending over and beyond the intersection of said second PN-junction at the second surface of said second semiconductor layer; wherein said second semiconductor region has an impurity concentration distribution in which the concentration of an impurity of said second conductivity type increases from said first PN-junction towards said second PN-junction; said first and third semiconductor regions are respectively provided with connections for supplying a voltage so as to reverse-bias said second PN-junction; and a Zener breakdown voltage of said second PN-junction is greater than a punch-through voltage between said first and third semiconductor regions.

Claim 21

A punch-through reference diode, comprising: a first semiconductor layer of P conductivity type having a relatively high impurity concentration and having first and second surfaces; and a second semiconductor layer disposed on said second surface of said first semiconductor layer, said second semiconductor layer having a first surface contacted with said second surface of said first semiconductor layer and a second surface opposite to said first surface of said second semiconductor layer, said second semiconductor layer comprising: p2 a first semiconductor region of P conductivity type having an impurity concentration less than that of said first semiconductor region being in contact with the second surface of said first semiconductor layer; a second semiconductor region of N conductivity type, said second semiconductor region adjoining said first semiconductor region and defining a first PN-junction with said first semiconductor region; a third semiconductor region of P conductivity type, said third semiconductor region adjoining said second semiconductor region and defining a second PN-junction with said second semiconductor region, whereby said second semiconductor region is located between said first PN-junction and said second PN-junction; a ring-shaped fourth semiconductor region, of P conductivity type and having a relatively high impurity concentration, surrounding and adjoining said second semiconductor region and extending from the second surface of said second semiconductor layer to the second surface of said first semiconductor layer; a ring-shaped fifth semiconductor region, of N conductivity type and having a relatively high impurity concentration, extending from said second surface of said second semiconductor layer and being contiguous with said second semiconductor region and said fourth semiconductor region; a ring-shaped electrode in ohmic contact, at the second surface of said second semiconductor layer, with said fourth and fifth semiconductor regions to short said first PN-junction; a bump-shaped electrode structure in ohmic contact with said third semiconductor region and extending over and beyond the intersection of said second PN-junction at the second surface of said second semiconductor layer; wherein said second semiconductor region has an impurity concentration distribution in which the concentration of an impurity of said second conductivity type increases from said first PN-junction towards said second PN-junction; said first and third semiconductor regions are respectively provided with connections for supplying a voltage so as to reverse-bias said second PN-junction; and a Zener breakdown voltage of said second PN-junction is greater than a punch-through voltage between said first and third semiconductor regions.

Claim 22

A punch-through reference diode according to claim 18, wherein said bump-shaped electrode structure is made of silver.