High voltage IC bipolar transistors operable to BVCBO and method of fabrication

Claim 2

An integrated circuit including bipolar and junction field effect transistors comprising: an N substrate; a PNP bipolar transistor in said substrate having a collector, base and emitter region; a P channel junction field effect transistor in said substrate having a channel region of the same depth and impurity concentration as said PNP collector region, source and drain regions of the same depth and impurity concentration as said PNP emitter region, a top gate region of the same depth and impurity concentration as said PNP base region and extending laterally beyond said channel region into said substrate and a buried N bottom gate region in said substrate of a high impurity concentration than said substrate and extending laterally beyond said channel region into said substrate to be connected to said top gate region by said substrate; and means for connecting said top gate and said base regions and means for connecting said source and said collector regions.

Claim 3

The integrated circuit according to claim 1, wherein said top gate region extends laterally beyond the portion of said channel region between said source and drain regions, and said bottom gate region extends laterally beyond said channel region in all lateral directions.

Claim 4

An integrated circuit including bipolar and junction field effect transistors comprising: an N substrate; an NPN bipolar transistor in said N substrate having a collector, base and emitter region; a PNP bipolar transistor in said substrate having a collector, base and emitter region; an N channel junction field effect transistor in said substrate having a channel region of the same depth and impurity concentration as said NPN collector region, source and drain regions having the same depth and impurity concentration as said NPN emitter region, a top gate having the same depth and impurity concentration as said NPN base region and extending laterally beyond said channel region, a buried P bottom gate region in said substrate extending laterally beyond said channel region and a lateral P region laterally surrounding said channel region and having the same depth and impurity concentration as said PNP collector region and connecting said top and bottom gate regions by a lower impurity region; and means for connecting said top gate and said base regions and means for connecting said source and said collector regions.

Claim 5

An integrated circuit including bipolar and junction field effect transistors comprising: an N substrate; an NPN bipolar transistor in said N substrate having a collector, base and emitter region; a PNP bipolar transistor in said substrate having a collector, base and emitter region; an N channel junction field effect transistor in said substrate having a channel region of the same depth and impurity concentration as said NPN collector region, source and drain regions having the same depth and impurity concentration as said NPN emitter region, a top gate having the same depth and impurity concentration as said NPN base region and extending laterally beyond said channel region, a buried P bottom gate region in said substrate extending laterally beyond said channel region and a lateral P region laterally surrounding said channel region and having the same depth and impurity concentration as said PNP collector region and connecting said top and bottom gate regions by a lower impurity region; and means for connecting said top gate and said base regions and means for connecting said source and said collector regions.

Claim 6

An integrated circuit according to claim 3, wherein said top gate extends laterally beyond the portion of said channel region between said source and drain regions, and said bottom gate region extends laterally beyond said channel region in all lateral directions.

Claim 7

An integrated circuit according to claim 3, wherein said N channel region and said NPN collector region are portions of said substrate.

Claim 8

An integrated circuit according to claim 3, including a P channel junction field effect transistor in said substrate having a channel region of the same depth and impurity concentration as said PNP collector region, source and drain regions having the same depth and impurity concentration as said PNP emitter region and a top gate having the same depth and impurity concentration as said PNP base region.

Claim 9

An integrated circuit according to claim 6 including means for connecting said P channel source and PHP collector regions, means for connecting said P channel gate and PNP base regions, means for connecting said N channel source and NPN collector regions, and means for connecting said N channel gate and NPN base regions.

Claim 10

An integrated circuit according to claim 3, wherein said lateral P region has a lower impurity concentration than said gate regions.

Claim 11

A bipolar transistor structure capable of operating to VB CBO comprising: a bipolar transistor having a base of a first conductivity type and an emitter and a collector of a second conductivity type opposite said first conductivity type; a junction field effect transistor having a top and bottom gate of said first conductivity type and a source, drain and channel of said second conductivity type; said channel and said collector have the same depth and impurity concentration and said top gate and said base have the same depth and impurity concentration; a connection region laterally encompassing said channel of said first conductivity type and lower impurity concentration than said gates, and extending from said bottom gate to a top surface adjacent said top gate; said gate being connected to said base and said source being connected to said collector.

Claim 12

A bipolar transistor structure capable of operating to VB CBO comprising: a bipolar transistor having a base of a first conductivity type and an emitter and a collector of a second conductivity type opposite said first conductivity type; a junction field effect transistor having a top and bottom gate of said first conductivity type and a source, drain and channel of said second conductivity type; said channel and said collector have the same depth and impurity concentration and said top gate and said base have the same depth and impurity concentration; a connection region laterally encompassing said channel of said first conductivity type and lower impurity concentration than said gates, and extending from said bottom gate to a top surface adjacent said top gate; said gate being connected to said base and said source being connected to said collector.

Claim 13

The integrated circuit according to claim 9, wherein said top gate region extends in at least one direction beyond said channel region into said a connecting region connecting said top and bottom gate regions.

Claim 14

An integrated circuit including bipolar transistors and junction field effect transistors comprising: a bipolar transistor including a collector region of a first depth, impurity concentration and conductivity type, a base region in said collector region of a second depth, impurity concentration and conductivity type, and an emitter region in siad base region of a third depth and impurity concentration and of said first conductivity type; a junction field effect transistor including a channel region of said first depth, impurity concentration and conductivity type; separate source and drain regions in said channel region of said third depth and impurity concentration and said first conductivity type; a top gate region in said channel region separating said source and drain regions of said second depth, impurity concentration and conductivity type; a buried bottom gate region of said second conductivity type and fourth impurity concentration; and a connecting region of said first conductivity type and a lower impurity concentration than said gates, laterally encompassing said channel region and extending from said bottom gate to a top surface adjacent said top gate; and means for connecting said gate regions to said base region and means for connecting said source region to said collector region.

Claim 15

An integrated circuit including bipolar transistors and junction field effect transistors comprising: a bipolar transistor including a collector region of a first depth, impurity concentration and conductivity type, a base region in said collector region of a second depth, impurity concentration and conductivity type, and an emitter region in siad base region of a third depth and impurity concentration and of said first conductivity type; a junction field effect transistor including a channel region of said first depth, impurity concentration and conductivity type; separate source and drain regions in said channel region of said third depth and impurity concentration and said first conductivity type; a top gate region in said channel region separating said source and drain regions of said second depth, impurity concentration and conductivity type; a buried bottom gate region of said second conductivity type and fourth impurity concentration; and a connecting region of said first conductivity type and a lower impurity concentration than said gates, laterally encompassing said channel region and extending from said bottom gate to a top surface adjacent said top gate; and means for connecting said gate regions to said base region and means for connecting said source region to said collector region.

Claim 16

The integrated circuit according to claim 11 including a second bipolar transistor having a collector region of said second conductivity type, a base region in said collector region of said first conductivity type and an emitter region in said base region of said second conductivity type; and wherein said connecting region has the same depth and impurity concentration as said collector of said second bipolar transistor.

Claim 17

The integrated circuit according to claim 11, wherein said top gate region extends laterally beyond said channel region in a direction transverse to the direction of separation of said source and drain regions into said connecting region.

Claim 18

The integrated circuit according to claim 11, wherein said bottom gate has a greater lateral area than said channel region and the bottom peripheral edge of said channel region terminates in said buried bottom gate region.