US4494134A Expired / Lapsed US ⏱️ 0.0 years remaining

High voltage semiconductor devices comprising integral JFET

Assignee: Intersil Corp

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Filing: 1982-07-01

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Granted: 1985-01-15

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Expires: 2002-07-01

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Abstract

Abstract A P-N diode includes a P - substrate with a thin N - epitaxial layer thereon. A P + isolation region surrounds the periphery of the N - epitaxial layer and is integrally connected to the P - substrate. An N + cathode region extends into the N - epitaxial layer from the upper surface of such layer. A P + anode region extends into the N - epitaxial layer from its upper surface and surrounds the N + cathode region. A further P + region extends into the N - epitaxial layer from its upper surface and surrounds the N + cathode region, and, in turn, is surrounded by the P + anode region. The further P + region is biased at the same potential as the P - substrate. An N + buried layer is situated between the P - substrate and the N - epitaxial layer, beneath the P + anode region, and surrounds the N.sup. + cathode region. An N + sinker region extends into the N - epitaxial layer from its upper surface and terminates in integral contact with the N + buried layer, the N + sinker region surrounding the P + anode region, and, in turn, being surrounded by the P + isolation region. The N + buried layer reduces parasitic currents in the P-N diode, and the further P + region, appropriately biased, enables the P-N diode to block current at high reverse voltages. An N-P-N transistor is structurally similar to the P-N diode, having an additional N + emitter region diffused into a P + base region, corresponding to the P + anode region of the P-N diode.

Inventors

👤 Eric J. Wildi
👤 Michael S. Adler

Bibliographic Details

Application Number —

Jurisdiction US

Data Source google_patents

Last Synchronized 2026-10-29 06:23

CPC Classifications

H; H10; H10D; H10D10/00; H10D10/40; H10D10/421; H10D62/00; H10D62/10; H10D62/102; H10D62/103; H10D62/105; H10D62/106; H10D8/00; H10D8/50; H10D84/00; H10D84/80; H10D84/811; H10W; H10W10/00; H10W10/01; H10W10/031; H10W10/30

Claims Analysis

Total Claims: 9

Claim 1

Independent Claim 193 words

ln a semiconductor device of the type including a bulk substrate of one dopant type, a layer of opposite dopant type disposed atop the substrate, an isolation region of same dopant type as the substrate integrally connected to the substrate and adjoining the periphery of the layer, a first region of the opposite dopant type extending into the layer from the interior of the upper surface thereof, and a second region of the one dopant type extending into the layer from the upper surface thereof and surrounding the first region, the improvement comprising (a) a third highly doped region of the opposite dopant type disposed between the layer and the substrate, beneath the second region and surrounding the first region; (b) a fourth region of the one dopant type extending into the layer from the upper surface thereof, the fourth region surrounding the first region and, in turn, being surrounded by the second region; and (c) means for biasing the fourth region to a potential proximate that of the substrate so as to increase the maximum attainable voltage between the first and second regions when the semiconductor device is in a current-blocking state.

Claim 2

Dependent Claim 193 words

Claim 3

Dependent Claim 50 words

The invention according to claim 1, further comprising a fifth region of the opposite dopant type extending into the layer from the upper surface thereof and terminating in integral contact with the third region, the fifth region surrounding the second region, and, in turn, being surrounded by the isolation region.

Claim 4

Dependent Claim 49 words

The invention of claim 2, further comprising a sixth region of the opposite dopant type extending into the layer from the upper surface thereof and terminating in integral contact with the third region, the sixth region surrounding the fourth region, and, in turn, being surrounded by the second region.

Claim 5

Dependent Claim 40 words

The invention of claim 1, further comprising an additional region of the opposite dopant type being disposed between the layer and the substrate, beneath the fourth region, surrounding the first region, and, in turn, being surrounded by the third region.

Claim 6

Dependent Claim 42 words

The invention according to claim 1 or 2, further comprising an additional region of the opposite dopant type formed entirely within the second region and extending into the second region from the upper surface thereof so as to surround the first region.

Claim 7

Dependent Claim 26 words

The invention according to claim 1, wherein the means for biasing the fourth region comprises a conductor connecting together the fourth region and the isolation region.

Claim 8

Dependent Claim 22 words

The invention according to claim 1, wherein the one dopant type is P type and the opposite dopant type is N type.

Claim 9

Dependent Claim 14 words

The invention according to claim 7, wherein the semiconductor device comprises silicon semiconductor material.

References Cited (Backward Citations)

US3878551A Cited

US3812405A Cited

JPS5367368A Cited

JPS5596675A Cited

JPS568874A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1988-01-15	1988-07-16	1989-01-15	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1992-01-15	1992-07-16	1993-01-15	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1996-01-15	1996-07-16	1997-01-15	$7700.00	Window Closed / Lapsed

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