US4150392A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated flip-flop circuit device including merged bipolar and field effect transistors
Assignee: Nippon Gakki Co Ltd
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Filing: 1977-07-29
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Granted: 1979-04-17
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Expires: 1997-07-29
Abstract
Abstract A semiconductor integrated circuit comprises a pair of load transistors and a pair of inverter transistors to constitute a flip-flop circuit. The load transistors are formed of p-channel field effect transistors serving as carrier injectors for the inverters formed of npn bipolar transistors. The p-type drain region of each load transistor is merged into the p-type base region of each inverter transistor. The absence of carrier storage effect in the field effect transistors improves the operation speed of the flip-flop remarkably and the high impedance gate electrode can be utilized as the clocking electrode to achieve clocking with voltage pulses without substantial power consumption. A plurality of such flip-flops are connected in cascode one after another to constitute a shift register.
Inventors
- 👤 Terumoto Nonaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 15:18
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/65; H10D84/655; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/411; G11C11/4113; G11C11/4116; G11C11/413; G11C11/414; G11C11/416; G11C19/00; G11C19/28; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/288; H10D84/40; H10D84/401; H10D84/403
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
425 words
A semiconductor integrated circuit device including at least one register cell formed in a monolithic semiconductor wafer which comprises a semiconductor substrate of a first conductivity type and a semiconductor layer of said first conductivity type disposed on said semiconductor substrate, the register cell including a master flip-flop circuit clocked by a first clock signal, and a slave flip-flop circuit inputted with the outputs of said master flip-flop circuit and clocked by a second clock signal of opposite phase to said first clock signal, each of said master and slave flip-flop circuits comprising: a first and a second bipolar transistor each having a base, a first and a second collector and an emitter; and a first and a second field effect transistor each having a drain, a gate and a source, the sources of both said first and second field effect transistors being merged in a first semiconductor region having a second conductivity type opposite to said first conductivity type and disposed in said semiconductor layer, the drain of said first field effect transistor and the base of said first bipolar transistor both being merged in a second semiconductor region of said second conductivity type disposed in said semiconductor layer, the drain of said second field effect transistor and the base of said second bipolar transistor both being merged in a third semiconductor region of said second conductivity type disposed in said semiconductor layer, the emitters of both said first and second bipolar transistors being merged in said semiconductor substrate, the first and second collectors of said first bipolar transistor being semiconductor regions of said first conductivity type disposed in said second semiconductor region, respectively, the first and second collectors of said second bipolar transistor being semiconductor regions of said first conductivity type disposed in said third semiconductor region, respectively, all of said first, second and third semiconductor regions being located adjacent to each other with no isolation layer intervening therebetween, the first collectors of said first and second bipolar transistors being connected to the drains of said second and first field effect transistors, respectively, the first clock signal being applied to both the gates of said first and second field effect transistors of said master flip-flop circuit, the second clock signal being applied to both the gates of said first and second field effect transistors of said slave flip-flop circuit, the second collectors of said first and second bipolar transistors of said master flip-flop circuit being connected to the first collectors of said first and second bipolar transistors of said slave flip-flop circuit, respectively.
Claim 2
Dependent Claim
425 words
A semiconductor integrated circuit device including at least one register cell formed in a monolithic semiconductor wafer which comprises a semiconductor substrate of a first conductivity type and a semiconductor layer of said first conductivity type disposed on said semiconductor substrate, the register cell including a master flip-flop circuit clocked by a first clock signal, and a slave flip-flop circuit inputted with the outputs of said master flip-flop circuit and clocked by a second clock signal of opposite phase to said first clock signal, each of said master and slave flip-flop circuits comprising: a first and a second bipolar transistor each having a base, a first and a second collector and an emitter; and a first and a second field effect transistor each having a drain, a gate and a source, the sources of both said first and second field effect transistors being merged in a first semiconductor region having a second conductivity type opposite to said first conductivity type and disposed in said semiconductor layer, the drain of said first field effect transistor and the base of said first bipolar transistor both being merged in a second semiconductor region of said second conductivity type disposed in said semiconductor layer, the drain of said second field effect transistor and the base of said second bipolar transistor both being merged in a third semiconductor region of said second conductivity type disposed in said semiconductor layer, the emitters of both said first and second bipolar transistors being merged in said semiconductor substrate, the first and second collectors of said first bipolar transistor being semiconductor regions of said first conductivity type disposed in said second semiconductor region, respectively, the first and second collectors of said second bipolar transistor being semiconductor regions of said first conductivity type disposed in said third semiconductor region, respectively, all of said first, second and third semiconductor regions being located adjacent to each other with no isolation layer intervening therebetween, the first collectors of said first and second bipolar transistors being connected to the drains of said second and first field effect transistors, respectively, the first clock signal being applied to both the gates of said first and second field effect transistors of said master flip-flop circuit, the second clock signal being applied to both the gates of said first and second field effect transistors of said slave flip-flop circuit, the second collectors of said first and second bipolar transistors of said master flip-flop circuit being connected to the first collectors of said first and second bipolar transistors of said slave flip-flop circuit, respectively.
Claim 3
Dependent Claim
76 words
A semiconductor integrated circuit device according to claim 1, in which: said first field effect transistor is an insulated gate type field effect transistor having a current channel formed in that portion of said semiconductor layer between said first and second semiconductor regions, and said second field effect transistor is an insulated gate type field effect transistor having a current channel formed in that portion of said semiconductor layer between said first and third semiconductor regions.
Claim 4
Dependent Claim
87 words
A semiconductor integrated circuit device according to claim 1, in which: all of said first, second and third semiconductor regions are merged in a common semiconductor region of said second conductivity type disposed in said semiconductor layer, and in which: said first and second field effect transistors are junction type field effect transistors, and each of the gates of said first and second field effect transistors is a semiconductor region of said first conductivity type disposed in said common semiconductor region adjacent to said first semiconductor region.
Claim 5
Dependent Claim
302 words
A semiconductor integrated circuit device including at least one flip-flop circuit formed in a monolithic semiconductor wafer, said monolithic wafer comprising a semiconductor substrate of a first conductivity type and a semiconductor layer of said first conductivity type disposed on said semiconductor substrate, said flip-flop circuit comprising: a first and a second bipolar transistor having a base, a collector and an emitter, respectively; and a first and a second field effect transistor having a drain, a gate and a source, respectively, the sources of both said first and second field effect transistors being merged in a first semiconductor region having a second conductivity type opposite to said first conductivity type and disposed in said semiconductor layer, the drain of said first field effect transistor and the base of said first bipolar transistor both being merged in a second semiconductor region of said second conductivity type disposed in said semiconductor layer, the drain of said second field effect transistor and the base of said second bipolar transistor both being merged in a third semiconductor region of said second conductivity type disposed in said semiconductor layer, the emitters of both said first and second bipolar transistors being merged in said semiconductor substrate, the collector of said first bipolar transistor being a semiconductor region of said first conductivity type disposed in said second semiconductor region, the collector of said second bipolar transistor being a semiconductor region of said first conductivity type disposed in said third semiconductor region, all of said first, second and third semiconductor regions being located adjacent to each other with no isolation layer intervening therebetween, the gates of both said first and second field effect transistors being connected together, the collectors of said first and second bipolar transistors being connected to the drains of said second and first field effect transistors, respectively.
Claim 6
Dependent Claim
302 words
A semiconductor integrated circuit device including at least one flip-flop circuit formed in a monolithic semiconductor wafer, said monolithic wafer comprising a semiconductor substrate of a first conductivity type and a semiconductor layer of said first conductivity type disposed on said semiconductor substrate, said flip-flop circuit comprising: a first and a second bipolar transistor having a base, a collector and an emitter, respectively; and a first and a second field effect transistor having a drain, a gate and a source, respectively, the sources of both said first and second field effect transistors being merged in a first semiconductor region having a second conductivity type opposite to said first conductivity type and disposed in said semiconductor layer, the drain of said first field effect transistor and the base of said first bipolar transistor both being merged in a second semiconductor region of said second conductivity type disposed in said semiconductor layer, the drain of said second field effect transistor and the base of said second bipolar transistor both being merged in a third semiconductor region of said second conductivity type disposed in said semiconductor layer, the emitters of both said first and second bipolar transistors being merged in said semiconductor substrate, the collector of said first bipolar transistor being a semiconductor region of said first conductivity type disposed in said second semiconductor region, the collector of said second bipolar transistor being a semiconductor region of said first conductivity type disposed in said third semiconductor region, all of said first, second and third semiconductor regions being located adjacent to each other with no isolation layer intervening therebetween, the gates of both said first and second field effect transistors being connected together, the collectors of said first and second bipolar transistors being connected to the drains of said second and first field effect transistors, respectively.
Claim 7
Dependent Claim
76 words
A semiconductor integrated circuit device according to claim 4, in which: said first field effect transistor is an insulated gate type field effect transistor having a current channel formed in that portion of said semiconductor layer between said first and second semiconductor regions, and said second field effect transistor is an insulated gate type field effect transistor having a current channel formed in that portion of said semiconductor layer between said first and third semiconductor regions.
Claim 8
Dependent Claim
87 words
A semiconductor integrated circuit device according to claim 4, in which: all of said first, second and third semiconductor regions are merged in a common semiconductor region of said second conductivity type disposed in said semiconductor layer, and in which: said first and second field effect transistors are junction type field effect transistors, and each of the gates of said first and second field effect transistors is a semiconductor region of said first conductivity type disposed in said common semiconductor region adjacent to said first semiconductor region.
Claim 9
Dependent Claim
58 words
A semiconductor integrated circuit device according to claim 4, in which: said first bipolar transistor has another collector which is a semiconductor region of said first conductivity type disposed in said second semiconductor region, and said second bipolar transistor has another collector which is a semiconductor region of said first conductivity type disposed in said third semiconductor region.
Claim 10
Dependent Claim
153 words
A semiconductor integrated circuit device according to claim 5, further comprising: a third and a fourth bipolar transistor each having a base, a collector and an emitter, the collector of said third bipolar transistor being merged in said second semiconductor region, the emitter of said third bipolar transistor being a fourth semiconductor region of said second conductivity type disposed in said semiconductor layer adjacent to said second semiconductor region, the base of said third bipolar transistor being a portion of said semiconductor layer between said second and fourth semiconductor regions, the collector of said fourth bipolar transistor being merged in said third semiconductor region, the emitter of said fourth bipolar transistor being a fifth semiconductor region of said second conductivity type disposed in said semiconductor layer adjacent to said third semiconductor region, the base of said fourth bipolar transistor being a portion of said semiconductor layer between said third and fifth semiconductor regions.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-04-16 | 1982-10-16 | 1983-04-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-04-16 | 1986-10-16 | 1987-04-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-04-16 | 1990-10-16 | 1991-04-17 | $7700.00 | Window Closed / Lapsed |