US4056810A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated injection logic memory circuit
Assignee: US Philips Corp
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Filing: 1976-01-28
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Granted: 1977-11-01
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Expires: 1996-01-28
Abstract
Abstract A new integrated circuit in which bias currents are supplied by means of a current injector, a multi-layer structure in which current is supplied, by means of injection and collection of charge carriers via rectifying junctions, to zones to be biased of circuit elements of the circuit, preferably in the form of charge carriers which are collected by the zones to be biased themselves from one of the layers of the current injector. By means of said current injector circuit arrangements can be realized without load resistors being necessary, while the wiring pattern may be very simple and the packing density of the circuit elements may be very high. In addition a simple method of manufacturing with comparatively few operations can in many cases be used in particular upon application of transistors having a structure which is inverted relative to the conventional structure.
Inventors
- 👤 Cornelis Maria Hart
- 👤 Arie Slob
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 03:47
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/091; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/411; G11C11/4113; G11C11/413; G11C11/414; H03F; H03F3/00; H03F3/04; H03K3/00; H03K3/01; H03K3/012; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/288; H03K3/289; H10; H10B; H10B10/00; H10B10/10; H10D; H10D48/00; H10D48/30; H10D48/32; H10D48/34; H10D48/345; H10D84/00; H10D84/60; H10D84/63; H10D84/65; H10D99/00; H04; H04R; H04R25/00; Y; Y10; Y10S; Y10S148/00; Y10S148/087
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
182 words
An integrated semiconductor memory comprising a plurality of groups of first, second, and third transistors each having emitter, base and collector, first and second transistors in each group being connected to form a plurality of cross-coupled trigger flip-flop circuits, said plurality of trigger circuits being arranged in rows and columns, the third transistors being complementary to the first and second transistors, a first read-write line commonly coupled to a column of trigger circuits, means connecting the first read-write line through the emitter-collector path of the third transistor to the base of the first transistor in that group, means for providing a circuit path from the emitters of the first and second transistors to a point of reference potential, a current injector coupled to the base zones of the first and second transistors and capable when forward biased of injecting carriers from a region outside of the first and second transistors and causing collection of the same or corresponding carriers by said base zones biasing the first and second transistors into operative condition, and a voltage supply line connected to the current injector.
Claim 2
Dependent Claim
182 words
An integrated semiconductor memory comprising a plurality of groups of first, second, and third transistors each having emitter, base and collector, first and second transistors in each group being connected to form a plurality of cross-coupled trigger flip-flop circuits, said plurality of trigger circuits being arranged in rows and columns, the third transistors being complementary to the first and second transistors, a first read-write line commonly coupled to a column of trigger circuits, means connecting the first read-write line through the emitter-collector path of the third transistor to the base of the first transistor in that group, means for providing a circuit path from the emitters of the first and second transistors to a point of reference potential, a current injector coupled to the base zones of the first and second transistors and capable when forward biased of injecting carriers from a region outside of the first and second transistors and causing collection of the same or corresponding carriers by said base zones biasing the first and second transistors into operative condition, and a voltage supply line connected to the current injector.
Claim 3
Dependent Claim
69 words
A memory as claimed in claim 1 wherein the plural groups each include a fourth transistor having emitter, base and collector and complementary to the first and second transistors, and further comprising a second read-write line commonly coupled to the column of trigger circuits, and means connecting the second read-write line through the emitter-collector path of the fourth transistor to the base of the second transistor in that group.
Claim 4
Dependent Claim
42 words
A memory as claimed in claim 2 and further comprising a common selection line for a row of trigger circuits, and means connecting the selection line to the base zones of the third and fourth transistors of a row of trigger circuits.
Claim 5
Dependent Claim
60 words
A memory as claimed in claim 2, wherein the current injector comprises a first layer and a second intermediate layer forming a P-N junction which when forward biased injects carriers collected by the base zones of the first and second transistors, said intermediate layer also constituting a common emitter zone for all the first and second transistors in a row.
Claim 6
Dependent Claim
26 words
A memory as claimed in claim 3, wherein the base zones connected to the selection line are constituted by a common region of a semiconductor body.
Claim 7
Dependent Claim
19 words
A memory as claimed in claim 4, wherein all of the groups are arrayed in a common semiconductor body.
Claim 8
Dependent Claim
205 words
An integrated semiconductor memory comprising a plurality of groups of first, second, third and fourth transistors each having emitter, base and collector, first and second transistors in each group being connected to form a plurality of cross-coupled trigger flip-flop circuits, said plurality of trigger circuits being arranged in rows and columns, means connecting the collector of the third and fourth transistors in each group to the bases respectively of the first and second transistors in the same group, first and second write lines commonly coupled to a column of trigger circuits, means for connecting the emitters of the first, second, third and fourth transistors to a point of reference potential, first and second current injectors each comprising means responsive to a forward bias for injecting carriers which when collected by a transistor zone will bias said zone into operation, a voltage supply line connected to the first current injector, means for coupling the first current injector to the base zones of the first and second transistors of all of the trigger circuits, a selection line connected to the second current injector, and means for coupling the second current injector to the base zones of the third and fourth transistors of a row of trigger circuits.
Claim 9
Dependent Claim
205 words
An integrated semiconductor memory comprising a plurality of groups of first, second, third and fourth transistors each having emitter, base and collector, first and second transistors in each group being connected to form a plurality of cross-coupled trigger flip-flop circuits, said plurality of trigger circuits being arranged in rows and columns, means connecting the collector of the third and fourth transistors in each group to the bases respectively of the first and second transistors in the same group, first and second write lines commonly coupled to a column of trigger circuits, means for connecting the emitters of the first, second, third and fourth transistors to a point of reference potential, first and second current injectors each comprising means responsive to a forward bias for injecting carriers which when collected by a transistor zone will bias said zone into operation, a voltage supply line connected to the first current injector, means for coupling the first current injector to the base zones of the first and second transistors of all of the trigger circuits, a selection line connected to the second current injector, and means for coupling the second current injector to the base zones of the third and fourth transistors of a row of trigger circuits.
Claim 10
Dependent Claim
95 words
An integrated semiconductor memory as claimed in claim 7, wherein each group further includes fifth and sixth transistors each having emitter, base and collector, means for connecting the emitters of the fifth and sixth transistors to the point of reference potential, means connecting the bases of the third and fourth transistors to the collectors of the fifth and sixth transistors, respectively, means connecting the bases of the fifth and sixth transistors to the first and second write lines, respectively, and means coupling the bases of the fifth and sixth transistors to the first current injector.
References Cited (Backward Citations)
US3801967A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-10-31 | 1981-05-02 | 1981-11-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-10-31 | 1985-05-02 | 1985-11-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-10-31 | 1989-05-02 | 1989-11-01 | $7700.00 | Window Closed / Lapsed |