Method of forming self-aligned implanted channel-stop and buried layer utilizing non-single crystal alignment key

Claim 1

A method for fabricating self-aligned buried doped regions in a semiconductor device, comprising: providing a semiconductor substrate having a device portion and an alignment key portion; covering a surface of said substrate with a first masking layer having a modifiable etch rate; covering said first layer with a second masking layer having first open portions exposing first portions of said first masking layer above first regions of said device portion of said substrate, and second open portions exposing second portions of said first masking layer located above first regions of said alignment key portion of said substrate; doping said first regions of said device portion of said substrate through said exposed first portions of said first masking layer; modifying said etch rate of said first and second portions of said first masking layer exposed in said first and second open portions of said second masking layer; creating holes in said first masking layer by removing those portions of said first masking layer whose etch rate has not been modified in the preceding steps, said holes in said first masking layer lying above second regions of said device portion and a key region of said alignment key portion of said substrate; doping said second regions of said device portion of said substrate through said holes in said first masking layer; rendering said key region of said alignment key portion of said substrate non-single crystal; exposing said surface of said substrate; forming a semiconductor layer on said surface of said substrate which is non-single crystal above said non-single crystal key region of said substrate and single crystal adjacent said non-single crystal key region and above said first and second regions of said device portion of said substrate.

Claim 2

A method for fabricating self-aligned buried doped regions in a semiconductor device, comprising: providing a semiconductor substrate having a device portion and an alignment key portion; covering a surface of said substrate with a first masking layer having a modifiable etch rate; covering said first layer with a second masking layer having first open portions exposing first portions of said first masking layer above first regions of said device portion of said substrate, and second open portions exposing second portions of said first masking layer located above first regions of said alignment key portion of said substrate; doping said first regions of said device portion of said substrate through said exposed first portions of said first masking layer; modifying said etch rate of said first and second portions of said first masking layer exposed in said first and second open portions of said second masking layer; creating holes in said first masking layer by removing those portions of said first masking layer whose etch rate has not been modified in the preceding steps, said holes in said first masking layer lying above second regions of said device portion and a key region of said alignment key portion of said substrate; doping said second regions of said device portion of said substrate through said holes in said first masking layer; rendering said key region of said alignment key portion of said substrate non-single crystal; exposing said surface of said substrate; forming a semiconductor layer on said surface of said substrate which is non-single crystal above said non-single crystal key region of said substrate and single crystal adjacent said non-single crystal key region and above said first and second regions of said device portion of said substrate.

Claim 12

A method for fabricating self-aligned buried doped regions in a semiconductor device, comprising: providing a single crystal semiconductor substrate having a device portion and an alignment key portion; covering a surface of said substrate with a first etch resistant layer; covering said first etch resistant layer with a polycrystalline semiconductor layer; forming a first masking layer on said polycrystalline semiconductor layer having first openings above said device portion and corresponding to the desired locations of a first of said buried doped regions, and second openings above said alignment key portions surrounding an alignment key region, wherein said first and second openings expose, respectively, first and second portions of said polycrystalline semiconductor layer; bombardment doping said substrate with first dopant ions of a first type and having energy sufficient to penetrate said polycrystalline semiconductor layer and said first etch resistant layer but not sufficient to penetrate said first masking layer, in order to dope said first of said buried doped regions through said first openings; doping said first and second portions of said polycrystalline semiconductor layer exposed in said first and second openings with a second dopant to a concentration sufficient to alter the etch rate of said first and second portions of said polycrystalline semiconductor layer; heating said polycrystalline semiconductor layer to laterally spread by predetermined amounts said second dopant placed in said exposed portions of said polycrystalline semiconductor layer, so as to produce enlarged first and second portions of said polycrystalline layer having altered etch rate; differentially etching said polycrystalline semiconductor layer to remove those parts of said polycrystalline layer lying outside said enlarged first and second portions; using remaining portions of said polycrystalline semiconductor layer as a mask, doping said substrate to form a second of said buried doped regions in said device portion of said substrate; covering said device portion of said substrate with a second masking layer that, in combination with remaining portions of said polycrystalline semiconductor layer, leaves accessible a key region in said alignment key portion of said substrate; rendering said key region in said alignment key portion of said substrate non-single crystal; exposing said surface of said substrate; growing a semiconductor layer on said substrate which is non-single crystal above said non-single crystal portion of said substrate and single crystal above said device portion of said substrate; and forming device regions in said single crystal portion of said semiconductor layer aligned with respect to said first and second buried doped regions using said polycrystalline portion of said semiconductor layer as an alignment key.

Claim 13

A method for fabricating self-aligned buried doped regions in a semiconductor device, comprising: providing a single crystal semiconductor substrate having a device portion and an alignment key portion; covering a surface of said substrate with a first etch resistant layer; covering said first etch resistant layer with a polycrystalline semiconductor layer; forming a first masking layer on said polycrystalline semiconductor layer having first openings above said device portion and corresponding to the desired locations of a first of said buried doped regions, and second openings above said alignment key portions surrounding an alignment key region, wherein said first and second openings expose, respectively, first and second portions of said polycrystalline semiconductor layer; bombardment doping said substrate with first dopant ions of a first type and having energy sufficient to penetrate said polycrystalline semiconductor layer and said first etch resistant layer but not sufficient to penetrate said first masking layer, in order to dope said first of said buried doped regions through said first openings; doping said first and second portions of said polycrystalline semiconductor layer exposed in said first and second openings with a second dopant to a concentration sufficient to alter the etch rate of said first and second portions of said polycrystalline semiconductor layer; heating said polycrystalline semiconductor layer to laterally spread by predetermined amounts said second dopant placed in said exposed portions of said polycrystalline semiconductor layer, so as to produce enlarged first and second portions of said polycrystalline layer having altered etch rate; differentially etching said polycrystalline semiconductor layer to remove those parts of said polycrystalline layer lying outside said enlarged first and second portions; using remaining portions of said polycrystalline semiconductor layer as a mask, doping said substrate to form a second of said buried doped regions in said device portion of said substrate; covering said device portion of said substrate with a second masking layer that, in combination with remaining portions of said polycrystalline semiconductor layer, leaves accessible a key region in said alignment key portion of said substrate; rendering said key region in said alignment key portion of said substrate non-single crystal; exposing said surface of said substrate; growing a semiconductor layer on said substrate which is non-single crystal above said non-single crystal portion of said substrate and single crystal above said device portion of said substrate; and forming device regions in said single crystal portion of said semiconductor layer aligned with respect to said first and second buried doped regions using said polycrystalline portion of said semiconductor layer as an alignment key.

Claim 15

A method for fabricating un-delineated buried doped regions in a semiconductor device, comprising: providing a semiconductor substrate having a device portion and an alignment key portion in a smooth first surface; covering said smooth first surface of said substrate with a first masking layer having a modifiable etch rate; covering said first masking layer with a second masking layer having first open portions exposing first portions of said first masking layer located above first regions of said device portion of said substrate, and second open portions exposing second portions of said first masking layer located above first regions of said alignment key portion of said substrate; doping said first regions of said device portion of said substrate through said exposed first portions of said first masking layer, without delineation of said first regions so that said device portion of said substrate remains smooth; modifying said etch rate of said first and second portions of said first masking layer exposed in said first and second open portions of said second masking layer; creating holes in said first masking layer by removing those portions of said first masking layer whose etch rate has not been modified in the preceding steps, said holes in said first masking layer lying above second regions of said device portion of said substrate and above a key portion of said alignment key portion of said substrate; doping said second regions of said device portion of said substrate through said holes in said first masking layer, without delineation of said second regions so that said device portion of said substrate remains smooth; rendering said key region of said alignment key portion of said substrate non-single crystal; exposing said surface of said substrate; forming a semiconductor layer on said surface of said substrate which is non-single crystal above said non-single crystal key region of said substrate and single crystal adjacent said non-single crystal key region; and forming a smooth single crystal semiconductor layer on said smooth surface of said device portion of said substrate, wherein said smooth single crystal semiconductor layer covers said first and second regions of said device ortion of said substrate without delineation.

Claim 16

A method for fabricating un-delineated buried doped regions in a semiconductor device, comprising: providing a semiconductor substrate having a device portion and an alignment key portion in a smooth first surface; covering said smooth first surface of said substrate with a first masking layer having a modifiable etch rate; covering said first masking layer with a second masking layer having first open portions exposing first portions of said first masking layer located above first regions of said device portion of said substrate, and second open portions exposing second portions of said first masking layer located above first regions of said alignment key portion of said substrate; doping said first regions of said device portion of said substrate through said exposed first portions of said first masking layer, without delineation of said first regions so that said device portion of said substrate remains smooth; modifying said etch rate of said first and second portions of said first masking layer exposed in said first and second open portions of said second masking layer; creating holes in said first masking layer by removing those portions of said first masking layer whose etch rate has not been modified in the preceding steps, said holes in said first masking layer lying above second regions of said device portion of said substrate and above a key portion of said alignment key portion of said substrate; doping said second regions of said device portion of said substrate through said holes in said first masking layer, without delineation of said second regions so that said device portion of said substrate remains smooth; rendering said key region of said alignment key portion of said substrate non-single crystal; exposing said surface of said substrate; forming a semiconductor layer on said surface of said substrate which is non-single crystal above said non-single crystal key region of said substrate and single crystal adjacent said non-single crystal key region; and forming a smooth single crystal semiconductor layer on said smooth surface of said device portion of said substrate, wherein said smooth single crystal semiconductor layer covers said first and second regions of said device ortion of said substrate without delineation.