Abstract An integrated circuit technique for passivating transistors and, at the same time, providing that the passivating material serve as part of the diffusion mask so as to avoid mask alignment difficulties, particularly the difficulty encountered when the steps of diffusing impurities and forming contact holes are to be performed in a very restricted area. The present technique involves the formation of a diffusion mask which is constituted of a film of a first material which is subject to ready etching by a first etchant but which is substantially unaffected by a second etchant; and of another, passivating, film which is constituted of a second material, the latter being subject to ready etching by the second etchant, but not by the first etchant. The first film is preferably made of silicon oxide (SiO2). The second film is preferably constituted of silicon nitride (Si3N4); however, other materials can be used for passivation, such as aluminum oxide (Al2O3). Only one etching step is required to be performed on the passivating film, whereby both the emitter window or opening and the base region contact openings are formed together. As a consequence, the mask alignment difficulties normally attending separate etching steps are obviated.
A method as defined in claim 1, further comprising the step of forming metalization to contact selectively the device region formed at said first opening and the substrate at said other openings.
Claim 2
Dependent Claim
16 words
forming at each selected device site a plurality of closely spaced openings in said second film;
Claim 3
Dependent Claim
77 words
extending at least one of said openings through said first film to reach the semiconductor substrate; d. selectively forming a device region at the semiconductor surface in said extended opening comprising diffusing in a sealed capsule an active impurity through said extended opening in said mask, the first film at said other openings being the sole layer acting to block said impurity. e. thereafter, extending said other openings through said first film to reach the semiconductor substrate.
Claim 4
Dependent Claim
21 words
A method as defined in claim 1, further comprising selectively removing any oxide formed by step (b) at said substrate surface.
Claim 5
Dependent Claim
68 words
A method as defined in claim 1 further comprising forming a photo-resist pattern over said second film and developing said pattern so as to form together all of the closely spaced openings required at each selected device site; forming successive individual photo-resist patterns to extend one of said openings in order to allow for diffusion of the impurity and to provide for contact formation at said other openings.
Claim 6
Dependent Claim
18 words
The method as defined in claim 1 in which step B comprises diffusing arsenic in a sealed capsule.
Claim 7
Dependent Claim
22 words
The method as defined in claim 1 in which said first layer is silicon oxide and said second layer is silicon nitride.
Claim 8
Dependent Claim
17 words
The method as defined in claim 6 wherein said first layer has a thickness of about 700A.