Input buffer circuit

Claim 1

The combination comprising: first and second insulated-gate field-effect transistors (IGFETs) of complementary conductivity type, each IGFET having source and drain electrodes defining the ends of a conduction path, and a control electrode; a signal input terminal, a signal output terminal, and first and second power terminals for the application therebetween of an operating potential; means connecting the control electrode of said second IGFET to said signal input terminal; means connecting the drain electrodes of said first and second IGFETs to said signal output terminal; means connecting said source of said first IGFET to said first power terminal; means connecting said source of said second IGFET to said second power terminal; selectively enabled level shift means coupled between the control electrodes of said second and first IGFETs for, in response to an input signal at said input terminal having a polarity and magnitude to turn-on said second IGFET, level shifting the input signal level and applying it to the control electrode of said second IGFET in a direction to reduce the forward bias between the control and source electrodes of said first IGFET; and means coupled between the output terminal and the control electrode of said first IGFET for turning-it off a predetermined period after its turn-on in response to an input signal at said input terminal of a polarity and magnitude to turn-off said second IGFET and turn-on said first IGFET.