US3832574A
Expired / Lapsed
US
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Fast insulated gate field effect transistor circuit using multiple threshold technology
Assignee: International Business Machines Corp
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Filing: 1972-12-29
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Granted: 1974-08-27
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Expires: 1992-12-29
Abstract
Abstract An integrated logic circuit using FETs having different threshold characteristics to assure that the FETs having the lower threshold voltage turn ON before those having a high threshold voltage when their gates are connected to a common node. Thus it is possible to use a low threshold FET diode as a series element in the discharge path between the logic output node of a conventional NOR circuit and its load. This diode isolates the conventional NOR from the interconnection capacitance, thus eliminating the effect of the interconnection capacitance on rising transitions at the logic output node. Furthermore, since low threshold devices can exist within the same circuit as the necessarily high threshold input FETs, two lower threshold FETs can be connected in series such that the input capacitance of a succeeding stage can be charged to a logic 1 voltage that is less than the power supply voltage by the gate to source voltage of the two lower threshold FETs. This logic 1 voltage is higher since the threshold of these two devices is lower than would be possible in single threshold technology. Also, the second of the two lower threshold FETs can serve as a charging means for the input capacitance of the succeeding stage while maintaining the isolation between that capacitance and the output of the conventional NOR circuit. Thus, multiple threshold technology can be used to reduce the effect of the interconnection capacitance of succeeding logic stages, while increasing the logic level.
Inventors
- 👤 G Leehan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 18:14
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/017
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
177 words
In an integrated logic circuit comprising a plurality of FETs on a single chip wherein at least two of said plurality of FETs have their gates connected to a common node, the improvement: a. wherein the first of said at least two of said plurality of FETs has a first threshold voltage, said first of said plurality of FETs having its gate and drain electrodes connected in common; and b. wherein the second of said at least two of said plurality of FETs has a second threshold voltage having the same polarity of said first threshold voltage, said second threshold voltage being greater in absolute magnitude than said first threshold voltage such that when the source of said first of said plurality of FETs is grounded the potential developed at the gate of said first of said plurality of FETs is equal to the threshold of said first of said plurality of FETs and below the threshold of said second of said plurality of FETs to cause said second of said plurality of FETs to cease conduction.
Claim 2
Dependent Claim
177 words
In an integrated logic circuit comprising a plurality of FETs on a single chip wherein at least two of said plurality of FETs have their gates connected to a common node, the improvement: a. wherein the first of said at least two of said plurality of FETs has a first threshold voltage, said first of said plurality of FETs having its gate and drain electrodes connected in common; and b. wherein the second of said at least two of said plurality of FETs has a second threshold voltage having the same polarity of said first threshold voltage, said second threshold voltage being greater in absolute magnitude than said first threshold voltage such that when the source of said first of said plurality of FETs is grounded the potential developed at the gate of said first of said plurality of FETs is equal to the threshold of said first of said plurality of FETs and below the threshold of said second of said plurality of FETs to cause said second of said plurality of FETs to cease conduction.
Claim 3
Dependent Claim
156 words
An integrated logic circuit comprising: a. a first FET having its gate connected to a first voltage source, its drain connected to a second voltage source, and its source connected to a first node; b. a second FET having its drain connected to said second voltage source, its gate connected to said first node and its source connected to a second node; c. a third FET having its gate and drain connected to said second node and its source connected to said first node; d. a plurality of input means connected to said first node; and e. a plurality of output means each including an input FET having its gate connected to said second node; and wherein the gate regions of said third FET and said input FETs are formed such that the threshold voltage of said third FET is the same polarity but less in absolute magnitude than the threshold voltage of said input FETs.
Claim 4
Dependent Claim
156 words
An integrated logic circuit comprising: a. a first FET having its gate connected to a first voltage source, its drain connected to a second voltage source, and its source connected to a first node; b. a second FET having its drain connected to said second voltage source, its gate connected to said first node and its source connected to a second node; c. a third FET having its gate and drain connected to said second node and its source connected to said first node; d. a plurality of input means connected to said first node; and e. a plurality of output means each including an input FET having its gate connected to said second node; and wherein the gate regions of said third FET and said input FETs are formed such that the threshold voltage of said third FET is the same polarity but less in absolute magnitude than the threshold voltage of said input FETs.
Claim 5
Dependent Claim
87 words
The integrated logic circuit as set forth in claim 2 wherein the gate voltage of said input FETs is the voltage on the interconnection capacitance between said second node and said input FET, whereby said interconnection capacitance is charged through said second FET when said second FET is ON, thereby turning ON said input FETs and said interconnection capacitance is discharged through said third FET and one of said input means when said one of said input means is turned ON thereby turning OFF said input FETs.
Claim 6
Dependent Claim
31 words
The integrated logic circuit as set forth in claim 3 wherein when said one of said input means turns ON, said second FET turns OFF and said third FET turns ON.
Claim 7
Dependent Claim
52 words
The integrated logic circuit as set forth in claim 4 wherein the ratio of conductance of the first FET to the input means is such that the voltage at said first node is less than the threshold voltage of said input FET minus the gate to source voltage of said third FET.
Claim 8
Dependent Claim
44 words
The integrated logic circuit as set forth in claim 5 wherein the width to length ratio of the gate of said second FET is relatively large whereby the voltage on the source of said second FET follows the rising voltage on said first node.
Claim 9
Dependent Claim
37 words
The integrated circuit as set forth in claim 3 wherein the conductance of said third FET is high such that the discharge time of said interconnection capacitance is a function of a conductance of said input means.
Claim 10
Dependent Claim
44 words
The integrated circuit as set forth in claim 2 wherein said input means comprises a plurality of FETs each having its drain connected to said first node wherein an input signal may be applied to the gates of any of said plurality of FETs.
Claim 11
Dependent Claim
41 words
The integrated circuit as set forth in claim 2 wherein the the threshold voltage of said first and second FETs is different from the threshold voltage of said input means whereby the logic 1 level at said second node is increased.
Claim 12
Dependent Claim
28 words
The integrated circuit as set forth in claim 2 wherein the conductance of said first FET is low and wherein quiescent power is dissipated in said first FET.
Claim 13
Dependent Claim
19 words
The integrated circuit as set forth in claim 2 wherein said input means is a parallel FET network means.
Claim 14
Dependent Claim
21 words
The integrated circuit as set forth in claim 2 wherein said first and second voltage sources are the same voltage source.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-08-26 | 1978-02-25 | 1978-08-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-08-26 | 1982-02-25 | 1982-08-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-08-26 | 1986-02-25 | 1986-08-27 | $7700.00 | Window Closed / Lapsed |