US3654623A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Binary memory circuit with coupled short term and long term storage means
Assignee: Signetics Corp
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Filing: 1970-03-12
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Granted: 1972-04-04
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Expires: 1990-03-12
Abstract
Abstract A binary memory circuit includes a short term memory having a capacitor coupled to a data bus by select and read and write field effect transistors. A long term memory element is also coupled to the capacitor and is in the form of a cross coupled inverter which includes gate-drain connected field effect transistors which act as load resistors in a pinch off mode for low power consumption. The switching time of the long term storage means is substantially longer than the rise time of the short term memory. The long term memory also restores or maintains any signal stored by the short term memory.
Inventors
- 👤 Eugene H Campbell
- 👤 James F Kane
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 20:26
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/405; G11C11/402; G11C11/4023; G11C11/41; G11C11/413; G11C11/417; G11C14/00
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
150 words
A binary memory circuit for storing two logic levels of a binary input logic signal comprising: short term storage means including a capacitor and responsive to said logic signal to store said logic levels in said capacitor said storage means having a relatively short response time to said logic signal as determined by said capacitor; and bistable switching means permanently coupled to said short term storage means switchable between two conditions and directly responsive to the Stored logic level of said logic signal in said storage means to assume a corresponding one of its two conditions and to maintain such stored level in said capacitor, the switching time of said switching means being long relative to said responsive time of said storage means said bistable switching means including cross coupled inverters coupled to a power supply each of said inverters being coupled to said power supply by separate resistor means.
Claim 2
Dependent Claim
150 words
A binary memory circuit for storing two logic levels of a binary input logic signal comprising: short term storage means including a capacitor and responsive to said logic signal to store said logic levels in said capacitor said storage means having a relatively short response time to said logic signal as determined by said capacitor; and bistable switching means permanently coupled to said short term storage means switchable between two conditions and directly responsive to the Stored logic level of said logic signal in said storage means to assume a corresponding one of its two conditions and to maintain such stored level in said capacitor, the switching time of said switching means being long relative to said responsive time of said storage means said bistable switching means including cross coupled inverters coupled to a power supply each of said inverters being coupled to said power supply by separate resistor means.
Claim 3
Dependent Claim
29 words
A binary memory circuit as in claim 1 in which said storage means has a discharge time relatively long compared to said switching time of said bistable switching means.
Claim 4
Dependent Claim
18 words
A binary memory circuit as in claim 1 in which said bistable switching mans includes cross coupled inverters.
Claim 5
Dependent Claim
24 words
A binary memory circuit as in claim 1 in which resistor means are field effect transistors having their gate and drain terminals tied together.
Claim 6
Dependent Claim
41 words
A binary memory circuit as in claim 1 where said capacitor is coupled to a data bus through a first field effect transistor driven by a select command and a second series coupled field effect transistor driven by a write command.
Claim 7
Dependent Claim
14 words
A binary memory circuit as in claim 1 where all circuit components are integrated.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-04-04 | 1975-10-04 | 1976-04-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-04-04 | 1979-10-04 | 1980-04-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-04-04 | 1983-10-04 | 1984-04-04 | $7700.00 | Window Closed / Lapsed |