US4080539A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Level shift circuit
Assignee: RCA Corp
•
Filing: 1976-11-10
•
Granted: 1978-03-21
•
Expires: 1996-11-10
Abstract
Abstract A gating means couples excitation signals to the input of an inverter which is connected between first and second power terminals. Positive feedback means is connected between the input and the output of the inverter. In response to an excitation signal, whose level is intermediate the levels of the operating voltages applied between the first and second power terminals, the inverter output is driven to the potential at one of the first and second power terminals while the potential at the other one of the first and second power terminals is applied to the inverter input. The gating means, conductive during transitions of the excitation signals from one level to another, does not conduct in the steady state condition, whereby a potential at the inverter input of higher amplitude than the excitation signals is not coupled back to the source of excitation signals.
Inventors
- 👤 Roger Green Stewart
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 18:20
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018521; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/3565
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
372 words
The combination comprising: first, second, and third power terminals for the application thereto of first, second, and third operating voltages, respectively; said second voltage having a value intermediate the values of said first and third voltages; an input node adapted to receive input signals making transitions between a first level, corresponding to said first voltage, and a second level; first and second inverters, each inverter having an input, an output, and two power terminals; means coupling said first and second power terminals to respective ones of said two power terminals of said first inverter; means connecting the input of said first inverter to said input node, the output of said first inverter being clamped to said first voltage when the input signal is at said second level and being clamped to said second voltage when the input signal is at said first level; means coupling said first and third power terminals to respective ones of said two power terminals of said second inverter; a first gating means connected between the output of said first inverter and the input of said second inverter for coupling to the input of the second inverter, via a low impedance path, the voltage transitions, at the output of the first inverter, going from said first voltage to said second voltage; said first means exhibiting a high impedance and being nonconductive when the output of said second inverter is at said first voltage and its input is at said third voltage; regenerative feedback means, connected between the output and the input of said second inverter, for driving the input of said second inverter to the voltage at said third power terminal and setting its output to the voltage at said first power terminal in response to the application to said second inverter of said transitions going from said first voltage to said second voltage; and a second gating means including a transistor having a conduction path and a control electrode, means connecting said control electrode to said input node and means connecting said conduction path between the input of said second inverter and said first power terminal for clamping the input of said second inverter to said first voltage when the input signal is at said second level.
Claim 2
Dependent Claim
372 words
The combination comprising: first, second, and third power terminals for the application thereto of first, second, and third operating voltages, respectively; said second voltage having a value intermediate the values of said first and third voltages; an input node adapted to receive input signals making transitions between a first level, corresponding to said first voltage, and a second level; first and second inverters, each inverter having an input, an output, and two power terminals; means coupling said first and second power terminals to respective ones of said two power terminals of said first inverter; means connecting the input of said first inverter to said input node, the output of said first inverter being clamped to said first voltage when the input signal is at said second level and being clamped to said second voltage when the input signal is at said first level; means coupling said first and third power terminals to respective ones of said two power terminals of said second inverter; a first gating means connected between the output of said first inverter and the input of said second inverter for coupling to the input of the second inverter, via a low impedance path, the voltage transitions, at the output of the first inverter, going from said first voltage to said second voltage; said first means exhibiting a high impedance and being nonconductive when the output of said second inverter is at said first voltage and its input is at said third voltage; regenerative feedback means, connected between the output and the input of said second inverter, for driving the input of said second inverter to the voltage at said third power terminal and setting its output to the voltage at said first power terminal in response to the application to said second inverter of said transitions going from said first voltage to said second voltage; and a second gating means including a transistor having a conduction path and a control electrode, means connecting said control electrode to said input node and means connecting said conduction path between the input of said second inverter and said first power terminal for clamping the input of said second inverter to said first voltage when the input signal is at said second level.
Claim 3
Dependent Claim
79 words
The combination as claimed in claim 1 wherein said first means includes an insulated-gate field-effect transistor (IGFET) having source and drain electrodes defining the ends of a conduction path and having a gate electrode whose applied potential determines the conductivity of said conduction path; said gate electrode being connected to the output of said second inverter, and the conduction path of said IGFET being connected between the output of said first inverter and said input of said second inverter.
Claim 4
Dependent Claim
62 words
The combination as claimed in claim 2 wherein said transistor of said second means is a second IGFET having its source-to-drain conduction path connected in parallel with the IGFET of said first means; and wherein the gate electrode of said second IGFET is said control electrode of said transistor; and wherein said first and second IGFETs are of the same conductivity type.
Claim 5
Dependent Claim
80 words
The combination as claimed in claim 3 wherein said first inverter includes regenerative feedback means coupled between its output and its input for driving said output of said first inverter to the voltage at one of its two power terminals and driving said input of said first inverter to the voltage at the other one of its two power terminals in response to a second level signal at said input node having a value intermediate said first and second voltages.
Claim 6
Dependent Claim
52 words
The combination as claimed in claim 2 wherein said transistor of said second means is an IGFET having its source-to-drain conduction path directly connected between said input of said second inverter and a point to which is applied said first operating voltage, and having its gate electrode connected to said input node.
Claim 7
Dependent Claim
31 words
The combination as claimed in claim 1 wherein said first means includes a unidirectionally conducting element connected between said output of said first inverter and said input of said second inverter.
Claim 8
Dependent Claim
44 words
The combination as claimed in claim 6 wherein said transistor of said second means is an insulated-gate field-effect transistor (IGFET) having its source-to-drain conduction path connected between said input of said second inverter and a point to which is applied said first operating voltage.
Claim 9
Dependent Claim
54 words
The combination as claimed in claim 6 wherein said transistor of said second means is an insulated-gate field-effect transistor (IGFET) having its source-to-drain conduction path connected between said output of said first inverter and said input of said second inverter; and wherein the gate electrode of said IGFET is connected to said input node.
Claim 10
Dependent Claim
228 words
A level shift circuit comprising: first, second, third and fourth power terminals for the application thereto of first, second, third and fourth operating voltages, respectively, the levels of said first and second voltages being intermediate the levels of said third and fourth voltages; an input node adapted to receive signals making transitions between first and second levels, intermediate the levels of said third and fourth operating voltages; first and second inverters, each inverter having an input and an output and two power terminals for the application therebetween of an operating voltage; means for applying said first and second voltages to respective ones of the two power terminals of the first inverter; means for applying the input of said first inverter to said input node; means for applying said third and fourth voltages to respective ones of the two power terminals of the second inverter; regenerative feedback means connected between the input and the output of said second inverter; and gating means comprising two parallel paths connected between the output of said first inverter and the input of said second inverter, each path including two IGFETs having their conduction paths connected in series; with the gate electrode of one transistor of each path being connected to the output of said second inverter and the gate electrode of the other transistor of each path being connected to said input node.
Claim 11
Dependent Claim
228 words
A level shift circuit comprising: first, second, third and fourth power terminals for the application thereto of first, second, third and fourth operating voltages, respectively, the levels of said first and second voltages being intermediate the levels of said third and fourth voltages; an input node adapted to receive signals making transitions between first and second levels, intermediate the levels of said third and fourth operating voltages; first and second inverters, each inverter having an input and an output and two power terminals for the application therebetween of an operating voltage; means for applying said first and second voltages to respective ones of the two power terminals of the first inverter; means for applying the input of said first inverter to said input node; means for applying said third and fourth voltages to respective ones of the two power terminals of the second inverter; regenerative feedback means connected between the input and the output of said second inverter; and gating means comprising two parallel paths connected between the output of said first inverter and the input of said second inverter, each path including two IGFETs having their conduction paths connected in series; with the gate electrode of one transistor of each path being connected to the output of said second inverter and the gate electrode of the other transistor of each path being connected to said input node.
Claim 12
Dependent Claim
38 words
The level shift circuit as claimed in claim 9 wherein one transistor in each of said parallel paths is of one conductivity type and the second transistor in each of said parallel paths is of opposite conductivity type.
Claim 13
Dependent Claim
55 words
The level shift circuit as claimed in claim 9 wherein said regenerative feedback means includes an inverting stage connected at its input to said output of said second inverter and connected at its output to said input of said second inverter and wherein said inverting stage is connected between said first and third operating voltages.
Claim 14
Dependent Claim
131 words
A level shift circuit comprising: a first inverter operated from a first operating voltage; a second inverter operated from a second operating voltage which exceeds the range of the first operating voltage; an input node adapted to receive input signals within the range of the first operating voltage; means connecting the input of the first inverter to the input node; a first transistor having its conduction path connected between the output of the first inverter and the input to the second inverter and having its control electrode connected to the output of the second inverter; and a second transistor having its conduction path connected between the input of the second inverter and one of the voltages providing said first operating voltage, and having its control electrode connected to the input node.
Claim 15
Dependent Claim
131 words
A level shift circuit comprising: a first inverter operated from a first operating voltage; a second inverter operated from a second operating voltage which exceeds the range of the first operating voltage; an input node adapted to receive input signals within the range of the first operating voltage; means connecting the input of the first inverter to the input node; a first transistor having its conduction path connected between the output of the first inverter and the input to the second inverter and having its control electrode connected to the output of the second inverter; and a second transistor having its conduction path connected between the input of the second inverter and one of the voltages providing said first operating voltage, and having its control electrode connected to the input node.
References Cited (Backward Citations)
US3675144A
Cited
US3654561A
Cited
US3842411A
Cited
DE2237579A1
Cited
US3823330A
Cited
US4000412A
Cited
US3906254A
Cited
US4006491A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-03-20 | 1981-09-19 | 1982-03-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-03-20 | 1985-09-19 | 1986-03-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-03-20 | 1989-09-19 | 1990-03-21 | $7700.00 | Window Closed / Lapsed |