US3906254A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Complementary FET pulse level converter
Assignee: International Business Machines Corp
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Filing: 1974-08-05
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Granted: 1975-09-16
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Expires: 1994-08-05
Abstract
Abstract An interfacing circuit for restoring voltage pulses to a desired fixed level. The circuit is particularly adapted to CMOS technology and includes features which result in rapid output rise and fall times, latching of the output voltage level, and isolation of the input following transition of the input voltage between its respective final levels. The circuit is also relatively insensitive to noise since it requires voltage transitions greater than the FET threshold levels to fully activate and switch the latching circuit means.
Inventors
- 👤 Ralph D Lane
- 👤 Richard A Manning
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 18:21
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018521
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
327 words
An interfacing circuit adapted to receive input voltage transitions of a relatively low level and provide corresponding output voltage transitions of a predetermined level comprising: a. an output node for said interfacing circuit and an input node for said interfacing circuit, b. a first n-channel FET and a second p-channel FET connected in series via their respective drain-source leads between a terminal of a power supply and a terminal at a reference potential, the series connection between said first and seCond FET''s being connected to said output node, c. latching circuit means having input and output nodes and being connected between said power supply and reference potentials, said latching means comprises; i. inverter means responsive to a variation in voltage at said latching circuit input node in a first and second direction to cause a variation in voltage at said latching circuit output node in a second and first direction, respectively, and ii. voltage variation increasing means responsive to the voltage connected at said latching circuit output node for increasing the variation of voltage at said latching circuit input node in the direction of initial variation at said latching circuit input node, whereby the further variation of the voltage at said latching circuit input node hard drives said inverter means to cause the voltage at said latching circuit output node to rapidly reach first or second predetermined final voltage values depending on the direction of variation of voltage at said latching circuit input and output nodes, d. means connecting said output node of said latching circuit means to the gate leads of said first and second FET''s, whereby the latching means output node voltage of said first predetermined value drives one of said FET''s on hard and drives the other FET off hard, and said second predetermined voltage value drives said other FET on hard and said one FET off hard, and e. input means connecting said interfacing circuit input node to said latching circuit input node.
Claim 2
Dependent Claim
327 words
An interfacing circuit adapted to receive input voltage transitions of a relatively low level and provide corresponding output voltage transitions of a predetermined level comprising: a. an output node for said interfacing circuit and an input node for said interfacing circuit, b. a first n-channel FET and a second p-channel FET connected in series via their respective drain-source leads between a terminal of a power supply and a terminal at a reference potential, the series connection between said first and seCond FET''s being connected to said output node, c. latching circuit means having input and output nodes and being connected between said power supply and reference potentials, said latching means comprises; i. inverter means responsive to a variation in voltage at said latching circuit input node in a first and second direction to cause a variation in voltage at said latching circuit output node in a second and first direction, respectively, and ii. voltage variation increasing means responsive to the voltage connected at said latching circuit output node for increasing the variation of voltage at said latching circuit input node in the direction of initial variation at said latching circuit input node, whereby the further variation of the voltage at said latching circuit input node hard drives said inverter means to cause the voltage at said latching circuit output node to rapidly reach first or second predetermined final voltage values depending on the direction of variation of voltage at said latching circuit input and output nodes, d. means connecting said output node of said latching circuit means to the gate leads of said first and second FET''s, whereby the latching means output node voltage of said first predetermined value drives one of said FET''s on hard and drives the other FET off hard, and said second predetermined voltage value drives said other FET on hard and said one FET off hard, and e. input means connecting said interfacing circuit input node to said latching circuit input node.
Claim 3
Dependent Claim
115 words
The interfacing circuit of claim 1 wherein said input means comprises: a. first circuit element means connected between said interfacing circuit input node and said latching circuit input node and responsive to a low voltage level at said interfacing circuit output node for providing a low resistance current path between said two input nodes, and b. second circuit element means connected between said two input circuit nodes and responsive to a high voltage level at said interfacing circuit output node for providing a low resistance current path between said two input nodes, and wherein said interfacing circuit further comprises a feedback connection between said interfacing circuit output node and said first and second circuit elements.
Claim 4
Dependent Claim
74 words
The interfacing circuit as claimed in claim 1 wherein said inverter means comprises, a third n-channel FET and a fourth p-channel FET connected in series via their drain-source leads between said power supply and reference terminals, said third and fourth FET''s having their gate leads connected together and to said latching circuit input node, the interconnection of said third and fourth FET''s in said series connection being connected to said latching circuit output node.
Claim 5
Dependent Claim
75 words
The interfacing circuit as claimed in claim 3 wherein said voltage variation increasing means comprises a fifth n-channel FET and a sixth p-channel FET connected in series via their drain-source leads between said power supply and reference terminals, said fifth and sixth FET''s having their gates connected together and to said latching circuit output node, the interconnection of said fifth and sixth FET''s in said series connection being connected to said latching circuit input node.
Claim 6
Dependent Claim
75 words
The interfacing circuit of claim 4 wherein said input means comprises: a. a seventh n-channel FET connected via its source-drain leads between said interfacing circuit input node and said latching circuit input node, b. an eighth p-channel FET connected via its source-drain leads between said interfacing circuit input node and said latching circuit input node, and c. a connection between said interfacing circuit output node and the gate leads of said seventh and eighth FET''s.
Claim 7
Dependent Claim
94 words
The interfacing circuit of claim 1 wherein said input means comprises means for isolating the interfacing circuit input node from the latching circuit input node at all times other than during the transition of sAid input and output voltages, and feedback means connected between said means for isolating and said interfacing circuit output node for preconditioning said means for isolating to provide a low resistance current path between said interfacing circuit input node and said latching circuit input node as soon as a transition occurs in the voltage at said interfacing circuit input node.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-09-15 | 1979-03-17 | 1979-09-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-09-15 | 1983-03-17 | 1983-09-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-09-15 | 1987-03-17 | 1987-09-16 | $7700.00 | Window Closed / Lapsed |