US3739200A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fet interface circuit
Assignee: LIEF A
•
Filing: 1971-09-27
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Granted: 1973-06-12
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Expires: 1991-09-27
Abstract
Abstract Field-effect transistor (FET) interface circuit for interfacing low power circuits with higher power circuits. The illustrated circuit employs complementary metal oxide semiconductor (C-MOS) devices to accomplish the interface function to a liquid crystal display element with minimal power dissipation and complexity.
Inventors
- 👤 Agostino M D
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 18:20
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018557; H03K19/018571; G; G04; G04G; G04G9/00; G04G9/0023; G04G9/0029; G04G9/0047; G09; G09G; G09G3/00; G09G3/04; G09G3/16; G09G3/18
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
321 words
A switching circuit responsive to a first source of bilevel input signal having relatively small amplitude swing to control the coupling of a second source of signal having a relatively larger amplitude value than either of the bilevel amplitude values to a load, said circuit comprising: first means for coupling said load and said second signal source in series with the source and drain leads of a first fieldeffect transistor; second means for coupling the source and drain leads of a second field-effect transistor between the source and the gate of the first transistor; an input control circuit coupled to the gate and drain leads of the second transistor and arranged to respond to one level of the input signal to turn said second transistor ''''on'''' such that the larger valued signal is applied to both the source and gate leads of the first transistor to thereby hold said first transistor in an ''''off'''' condition, said control circuit also responding to a change from said one to the other level of said input signal to turn the first transistor ''''on;'''' said control circuit including third and fourth field-effect transistors, the source and drain leads of the third transistor being coupled between the gate lead of the second transistor and the first signal source, the gate lead of the third transistor being coupled to a bias source, the source and drain leads of the fourth transistor being coupled between the gate lead of the first transistor and a point of reference potential, and the gate lead of the fourth transistor being coupled to said first signal source; and a feedback path coupled between the drain lead of the first transistor and gate lead of the second transistor and arranged to respond to the ''''on'''' condition of tHe first transistor to charge the parasitic capacitance associated with the gate lead of the second transistor to a value which renders the second transistor nonconductive.
Claim 2
Dependent Claim
321 words
A switching circuit responsive to a first source of bilevel input signal having relatively small amplitude swing to control the coupling of a second source of signal having a relatively larger amplitude value than either of the bilevel amplitude values to a load, said circuit comprising: first means for coupling said load and said second signal source in series with the source and drain leads of a first fieldeffect transistor; second means for coupling the source and drain leads of a second field-effect transistor between the source and the gate of the first transistor; an input control circuit coupled to the gate and drain leads of the second transistor and arranged to respond to one level of the input signal to turn said second transistor ''''on'''' such that the larger valued signal is applied to both the source and gate leads of the first transistor to thereby hold said first transistor in an ''''off'''' condition, said control circuit also responding to a change from said one to the other level of said input signal to turn the first transistor ''''on;'''' said control circuit including third and fourth field-effect transistors, the source and drain leads of the third transistor being coupled between the gate lead of the second transistor and the first signal source, the gate lead of the third transistor being coupled to a bias source, the source and drain leads of the fourth transistor being coupled between the gate lead of the first transistor and a point of reference potential, and the gate lead of the fourth transistor being coupled to said first signal source; and a feedback path coupled between the drain lead of the first transistor and gate lead of the second transistor and arranged to respond to the ''''on'''' condition of tHe first transistor to charge the parasitic capacitance associated with the gate lead of the second transistor to a value which renders the second transistor nonconductive.
Claim 3
Dependent Claim
23 words
The invention as set forth in claim 1 wherein said feedback path includes a fifth field-effect transistor arranged in a source follower configuration.
Claim 4
Dependent Claim
33 words
The invention as set forth in claim 2 wherein said first and second transistors are of a first conductivity type and the third, fourth and fifth transistors are of a second conductivity type.
Claim 5
Dependent Claim
27 words
The invention as set forth in claim 3 wherein said first coupling means includes a diode connected between the source leads of the first and second transistors.
Claim 6
Dependent Claim
87 words
The invention as set forth in claim 4 wherein said load is one of a plurality of loads, said first source is one of a like plurality of such sources, and said switching circuit is one of a like plurality of such circuits which are arranged to respond to different ones of the first source to couple said second signal source to corresponding ones of said loads; and wherein the first coupling means all said switching circuits includes a diode circuit shared by all said switching circuits.
Claim 7
Dependent Claim
19 words
The invention as set forth in claim 5 wherein said loads comprise different plates of a liquid crystal display.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-06-11 | 1976-12-11 | 1977-06-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-06-11 | 1980-12-11 | 1981-06-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-06-11 | 1984-12-11 | 1985-06-12 | $7700.00 | Window Closed / Lapsed |