US3755690A
Expired / Lapsed
US
⏱️ 0.0 years remaining
M.o.s. input circuit with t. t. l. compatability
Assignee: Standard Microsystems LLC
•
Filing: 1972-06-06
•
Granted: 1973-08-28
•
Expires: 1992-06-06
Abstract
Abstract A circuit for interfacing between the output of a TTL circuit and the input of an MOS circuit is described which utilizes a switchable pull-up resistor connected between the TTL circuit output and a voltage line to translate the level of the TTL output to a level compatible with the requirements of the MOS circuit.
Inventors
- 👤 F Smith
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 16:48
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
204 words
An interface circuit for coupling between a first logic stage having a first range of output signal levels and a second logic stage employing input signal levels different than said first stage output signal levels, said interface circuit comprising an input node for coupling to the output of the first logic stage and an output node for coupling to the input of the second logic stage, a voltage line at a level corresponding to one of the second logic stage signal levels, switching means having a control element and an output circuit coupled between said voltage line and said input node and effective when conductive to establish said output node at a first logic level, and when nonconductive to establish said output node at a second logic level, and control means coupled to said input node for controlling the conductive state of said switching means, said control means comprises second switching means having a control element coupled to said input node and an output circuit coupled to said voltage line and to the control element of said first named switching means, said output node being coupled to the output circuit of said second switching means and the control element of said first switching means.
Claim 2
Dependent Claim
204 words
An interface circuit for coupling between a first logic stage having a first range of output signal levels and a second logic stage employing input signal levels different than said first stage output signal levels, said interface circuit comprising an input node for coupling to the output of the first logic stage and an output node for coupling to the input of the second logic stage, a voltage line at a level corresponding to one of the second logic stage signal levels, switching means having a control element and an output circuit coupled between said voltage line and said input node and effective when conductive to establish said output node at a first logic level, and when nonconductive to establish said output node at a second logic level, and control means coupled to said input node for controlling the conductive state of said switching means, said control means comprises second switching means having a control element coupled to said input node and an output circuit coupled to said voltage line and to the control element of said first named switching means, said output node being coupled to the output circuit of said second switching means and the control element of said first switching means.
Claim 3
Dependent Claim
40 words
The circuit of claim 1, further comprising resistor means coupled between the output circuit of said first switching means and an intermediate node, the latter being coupled to said input node and the control element of said second switching means.
Claim 4
Dependent Claim
19 words
The circuit of claim 2, further comprising second resistor means coupled between said input node and said intermediate node.
Claim 5
Dependent Claim
34 words
The circuit of claim 1, in which said output logic stage is a TTL stage and said input stage is an MOS stage, said first and second switching means each comprising an MOS FET.
References Cited (Backward Citations)
US3602732A
Cited
US3676700A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-08-27 | 1977-02-26 | 1977-08-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-08-27 | 1981-02-26 | 1981-08-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-08-27 | 1985-02-26 | 1985-08-28 | $7700.00 | Window Closed / Lapsed |