US4342928A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit and method for voltage level conversion
Assignee: International Business Machines Corp
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Filing: 1980-07-07
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Granted: 1982-08-03
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Expires: 2000-07-07
Abstract
Abstract A known FET driver circuit which is to be controlled at the gate by means of relatively low TTL signals, is improved in such a manner that the source potential of the input transistors is shifted oppositely to the input signal. This leads to an increase in the effective potential difference in the signal level applied to the input transistors and thus to an improved switching speed.
Inventors
- 👤 Jorg Gschwendtner
- 👤 Wolfdieter Lohlein
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 08:50
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/01; H03K19/017; H03K19/01707; H03K19/01714
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
181 words
A field-effect transistor input buffer circuit for converting low level binary logic input signals applied to an input node to high level binary logic output signals delivered to an output node, the input signals having predefined up and down logic levels, each of the up and down levels being defined over a range of voltages, comprising: a source bias node; a first field-effect transistor having gate, drain and source electrodes, the gate electrode being connected to the input node, the drain electrode being connected to the output node and the source electrode being connected to said source bias node, and source bias control means responsive to signals on the input node for changing the potential on said source bias node to increase the gate-to-source voltage of said first transistor to a voltage greater than the voltage of an up level input signal in response to an up level input signal and to decrease the gate-to-source voltage of said first transistor to a voltage less than the voltage of a down level input signal in response to a down level input signal.
Claim 2
Dependent Claim
181 words
A field-effect transistor input buffer circuit for converting low level binary logic input signals applied to an input node to high level binary logic output signals delivered to an output node, the input signals having predefined up and down logic levels, each of the up and down levels being defined over a range of voltages, comprising: a source bias node; a first field-effect transistor having gate, drain and source electrodes, the gate electrode being connected to the input node, the drain electrode being connected to the output node and the source electrode being connected to said source bias node, and source bias control means responsive to signals on the input node for changing the potential on said source bias node to increase the gate-to-source voltage of said first transistor to a voltage greater than the voltage of an up level input signal in response to an up level input signal and to decrease the gate-to-source voltage of said first transistor to a voltage less than the voltage of a down level input signal in response to a down level input signal.
Claim 3
Dependent Claim
43 words
The input buffer circuit of claim 1 wherein said source bias control means comprises a resistive element connected between said source bias node and a voltage source having a potential which is less than the voltage level of a down level input signal.
Claim 4
Dependent Claim
22 words
The input buffer circuit of claim 2 wherein said voltage source is a substrate bias voltage for said first field effect transistor.
Claim 5
Dependent Claim
14 words
The input buffer of claim 3 wherein said resistive element is a semiconductor resistor.
Claim 6
Dependent Claim
56 words
The input buffer of claim 1 wherein said source bias control means comprises a second field effect transistor connected between said source bias node and a voltage source having a potential greater than the voltage level of an up level input signals, said second field-effect transistor being responsive to a signal out-of-phase with the input signal.
Claim 7
Dependent Claim
33 words
The input buffer circuit of claim 5 wherein said source bias control means includes a field-effect transistor inverter circuit including a third field-effect transistor having its gate electrode connected to the input node.
Claim 8
Dependent Claim
47 words
The input buffer circuit of claim 1 wherein said source bias control means comprises a field-effect transistor bootstrap inverter circuit driver responsive to the input signal and having its output coupled to a source-follower coupled field-effect amplifier, the output of which is connected to said bias node.
Claim 9
Dependent Claim
98 words
The input buffer circuit of claim 7 further including a second field-effect transistor having its gate electrode connected to the input node, its source electrode connected to said source bias node and its drain connected to the source of a third field-effect transistor, a bootstrap capacitor coupled between the gate and source electrodes of the third transistor and a fourth field-effect transistor having its source connected to the output node, the gates of the third and fourth transistors being common and the drain electrodes of the third and fourth transistors connected to a field-effect transistor power supply source.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-08-02 | 1986-02-01 | 1986-08-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-08-02 | 1990-02-01 | 1990-08-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-08-02 | 1994-02-01 | 1994-08-03 | $7700.00 | Window Closed / Lapsed |