US4303933A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Self-aligned micrometer bipolar transistor device and process
Assignee: International Business Machines Corp
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Filing: 1979-11-29
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Granted: 1981-12-01
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Expires: 1999-11-29
Abstract
Abstract A method for device fabrication disclosed is a self-aligned process. The device formed has small vertical as well as horizontal dimensions. The device region is surrounded by a deep oxide trench which has nearly vertical sidewalls. The deep trench extends from the epitaxial silicon surface through N+ subcollector region into the P substrate. The width of the deep trench is about 2 μm to 3.0 μm. A shallow oxide trench extending from the epitaxial silicon surface to the upper portion of the N+ subcollector separates the base and collector contact. The surface of the isolation regions and the silicon where the transistor is formed is coplanar. As shown in FIG. 1, the fabricated bipolar transistor has a mesa-type structure. The transistor base dimension is only slightly larger than the emitter. This small base area results in low collector-base capacitance which is a very important parameter in ultra-high performance integrated circuit devices. Contact to the transistor base in the disclosed structure is achieved by a thick heavily boron doped polysilicon layer which surrounds the emitter and makes lateral contact to the active base.
Inventors
- 👤 Cheng T. Horng
- 👤 Michael R. Poponiak
- 👤 Hans S. Rupprecht
- 👤 Robert O. Schwenker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 23:25
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/021; H10D; H10D10/00; H10D10/40; H10D10/441; H10D62/00; H10D62/10; H10D62/13; H10D62/133; H10D62/17; H10D62/177; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0143; H10W10/0145; H10W10/10; H10W10/17; Y; Y10; Y10S; Y10S148/00; Y10S148/131
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
306 words
In an integrated circuit device a planar self-aligned vertical bipolar transistor structure, said structure comprising: a monolithic silicon substrate; a shallow depth silicon epitaxial layer upon one surface of said substrate, said epitaxial layer having a substantially flat exposed top surface; an emitter region formed in said epitaxial layer, said emitter region having an exposed essentially planar surface, said exposed planar surface of said emitter region being co-planar with said substantially flat exposed top surface of said epitaxial layer; a base region formed in said epitaxial layer beneath said emitter region to provide a base-emitter junction, said base-emitter junction being essentially flat and having a predetermined area; a collector region having a vertical portion formed beneath said base region to provide a base-collector junction and said collector region also having a lateral portion integrally formed with said vertical portion, said lateral portion of said collector region lying beneath and extending from said vertical portion of said collector region, said base-collector junction being essentially flat and having an area substantially equal to said predetermined area of said base-emitter junction and residing directly beneath and uniformly spaced from said base-emitter junction; a polysilicon region of relatively high conductivity laterally encompassing said emitter region, said base region and said vertical portion of said collector region and said polysilicon region extending laterally above said lateral portion of said collector region; insulator means including a vertical portion for electrically isolating said polysilicon region from said emitter region, said base-emitter junction, said vertical portion of said collector region and said base-collector junction, said insulator means also including a lateral portion integral with at least a portion of said vertical portion thereof, said lateral portion of said insulator means electrically isolating said polysilicon region from said lateral portion of said collector region and, said polysilicon region providing electrical contact to said base region.
Claim 2
Dependent Claim
306 words
In an integrated circuit device a planar self-aligned vertical bipolar transistor structure, said structure comprising: a monolithic silicon substrate; a shallow depth silicon epitaxial layer upon one surface of said substrate, said epitaxial layer having a substantially flat exposed top surface; an emitter region formed in said epitaxial layer, said emitter region having an exposed essentially planar surface, said exposed planar surface of said emitter region being co-planar with said substantially flat exposed top surface of said epitaxial layer; a base region formed in said epitaxial layer beneath said emitter region to provide a base-emitter junction, said base-emitter junction being essentially flat and having a predetermined area; a collector region having a vertical portion formed beneath said base region to provide a base-collector junction and said collector region also having a lateral portion integrally formed with said vertical portion, said lateral portion of said collector region lying beneath and extending from said vertical portion of said collector region, said base-collector junction being essentially flat and having an area substantially equal to said predetermined area of said base-emitter junction and residing directly beneath and uniformly spaced from said base-emitter junction; a polysilicon region of relatively high conductivity laterally encompassing said emitter region, said base region and said vertical portion of said collector region and said polysilicon region extending laterally above said lateral portion of said collector region; insulator means including a vertical portion for electrically isolating said polysilicon region from said emitter region, said base-emitter junction, said vertical portion of said collector region and said base-collector junction, said insulator means also including a lateral portion integral with at least a portion of said vertical portion thereof, said lateral portion of said insulator means electrically isolating said polysilicon region from said lateral portion of said collector region and, said polysilicon region providing electrical contact to said base region.
Claim 3
Dependent Claim
29 words
In an integrated circuit device a planar vertical transistor structure as recited in claim 1 wherein said insulator means being a composite layer of silicon dioxide and silicon nitride.
Claim 4
Dependent Claim
30 words
In an integrated circuit device a planar vertical transistor structure as recited in claim 2 wherein the silicon nitride of said composite layer has a thickness of approximately 1,000 A.
Claim 5
Dependent Claim
421 words
In an integrated circuit device a planar vertical bipolar transistor structure (FIGS. 1A, 1B and 1C), said structure comprising: a monolithic silicon substrate 10; a shallow depth silicon epitaxial layer 12 upon one surface of said substrate, said epitaxial layer having a substantially flat exposed top surface; an emitter region 29 formed in said epitaxial layer, said emitter region having an exposed essentially planar surface, said exposed essentially planar surface of said emitter region being co-planar with said substantially flat exposed top surface of said epitaxial layer; a base region 44 formed in said epitaxial layer beneath said emitter region to provide a base-emitter junction; a collector region 11, said collector region having a vertically extending portion and a laterally extending portion, said vertically extending portion lying beneath said base region to provide a base-collector junction, said laterally extending portion of said collector region being integrally formed with said vertical portion of said collector region, said laterally extending portion of said collector region lying beneath and laterally extending from said vertical portion of said collector region; said base-emitter junction being essentially flat and having a predetermined area, said base-collector junction residing directly beneath and uniformly spaced from said base-emitter junction, and said base-collector junction being essentially flat and coextensive in area with said base-emitter junction; a polysilicon region 39 of relatively high conductivity laterally encompassing said emitter region, said base region, said base-emitter junction, said vertically extending portion of said collector region and said base-collector junction, said lateral polysilicon region providing electrical contact to said base region; and, insulator means 33, 38 electrically isolating said polysilicon region from said emitter region, said base-emitter junction, said collector region and said base-collector junction, said insulator means including a generally cylindrical vertical portion and a lateral portion, said lateral portion being integrally formed with at least a portion of said generally cylindrical vertical portion, said lateral portion lying beneath and laterally extending from said generally cylindrical vertical portion, said generally cylindrical vertical portion of said insulator means electrically isolating said emitter region, said base-emitter junction, said base-collector junction and said vertically extending portion of said collector region from said lateral polysilicon region, and said lateral portion of said insulator means electrically isolating said laterally extending portion of said collector region from said lateral polysilicon region, said generally cylindrical vertical portion of said insulator means comprising a silicon dioxide layer 33 having a thickness in the order of 2,000 A and a silicon nitride layer 38 having a thickness in the order of 1,000 A.
Claim 6
Dependent Claim
421 words
In an integrated circuit device a planar vertical bipolar transistor structure (FIGS. 1A, 1B and 1C), said structure comprising: a monolithic silicon substrate 10; a shallow depth silicon epitaxial layer 12 upon one surface of said substrate, said epitaxial layer having a substantially flat exposed top surface; an emitter region 29 formed in said epitaxial layer, said emitter region having an exposed essentially planar surface, said exposed essentially planar surface of said emitter region being co-planar with said substantially flat exposed top surface of said epitaxial layer; a base region 44 formed in said epitaxial layer beneath said emitter region to provide a base-emitter junction; a collector region 11, said collector region having a vertically extending portion and a laterally extending portion, said vertically extending portion lying beneath said base region to provide a base-collector junction, said laterally extending portion of said collector region being integrally formed with said vertical portion of said collector region, said laterally extending portion of said collector region lying beneath and laterally extending from said vertical portion of said collector region; said base-emitter junction being essentially flat and having a predetermined area, said base-collector junction residing directly beneath and uniformly spaced from said base-emitter junction, and said base-collector junction being essentially flat and coextensive in area with said base-emitter junction; a polysilicon region 39 of relatively high conductivity laterally encompassing said emitter region, said base region, said base-emitter junction, said vertically extending portion of said collector region and said base-collector junction, said lateral polysilicon region providing electrical contact to said base region; and, insulator means 33, 38 electrically isolating said polysilicon region from said emitter region, said base-emitter junction, said collector region and said base-collector junction, said insulator means including a generally cylindrical vertical portion and a lateral portion, said lateral portion being integrally formed with at least a portion of said generally cylindrical vertical portion, said lateral portion lying beneath and laterally extending from said generally cylindrical vertical portion, said generally cylindrical vertical portion of said insulator means electrically isolating said emitter region, said base-emitter junction, said base-collector junction and said vertically extending portion of said collector region from said lateral polysilicon region, and said lateral portion of said insulator means electrically isolating said laterally extending portion of said collector region from said lateral polysilicon region, said generally cylindrical vertical portion of said insulator means comprising a silicon dioxide layer 33 having a thickness in the order of 2,000 A and a silicon nitride layer 38 having a thickness in the order of 1,000 A.
References Cited (Backward Citations)
US3600651A
Cited
US3631307A
Cited
US3648125A
Cited
US3947299A
Cited
US3796613A
Cited
US3919005A
Cited
US3873372A
Cited
US3904450A
Cited
GB1514624A
Cited
US3958323A
Cited
US3961999A
Cited
US4011105A
Cited
US4048649A
Cited
US4103415A
Cited
US4195307A
Cited
US4104086A
Cited
US4139442A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-11-30 | 1985-06-01 | 1985-12-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-11-30 | 1989-06-01 | 1989-12-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-11-30 | 1993-06-01 | 1993-12-01 | $7700.00 | Window Closed / Lapsed |