Abstract A semiconductor device which utilizes a nonplanar structure to provide for an increased power capability and an improved highfrequency performance. A multiplicity of emitter regions are isolated on plateaus wherein each plateau is surrounded by a moat. A base region forms a PN junction with each emitter region, which junction extends to the edge of the moat. The base region has a portion which extends toward the base of the moat within the periphery of the plateau. An insulated base electrode is placed within the moat so as to make contact with the base region beneath the surface of the device, while contact is made to the emitter region by a metal layer extending over a portion of the device surface. This configuration provides for an increased emitter periphery for a given base area and thus improved highfrequency performance and power capability.
A semiconductor device according to claim 1 wherein second dielectric layers are disposed over said first metal layers and are contiguous with said second PN-junction.
Claim 2
Dependent Claim
27 words
A semiconductor device according to claim 2 wherein said second metal layer is disposed over each said discrete emitter region and extends over said second dielectric layers.
Claim 3
Dependent Claim
15 words
A semiconductor device according to claim 1 wherein said first metal layers are of palladium.
Claim 4
Dependent Claim
18 words
A semiconductor device according to claim 2 wherein said first and second dielectric layers are of silicon dioxide.
Claim 5
Dependent Claim
66 words
A semiconductor device according to claim 1 wherein all of said plateaus are located along one part of the surface of said body, said second metal layer extends continuously over said part to form an emitter electrode of said device, and one of said first metal layers extending to a section of the remaining part of the surface of said body to form a base electrode.