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US3919005A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for fabricating double-diffused, lateral transistor

Assignee: Fairchild Semiconductor Corp
•
Filing: 1974-07-01
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Granted: 1975-11-11
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Expires: 1994-07-01
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Abstract

Abstract A double-diffused, lateral transistor structure is fabricated utilizing an etch resistant mask to provide self-aligning positional accuracy for formation of active areas of the transistor. The lateral structure includes semiconductor material having at least one substantially flat surface, and the structure includes at least one region of insulating material formed adjacent the flat surface, the top surface of the insulating material being substantially coplanar with said one surface. A collector is formed in the semiconductor material adjacent first portions of both the flat surface and the insulating material, while an emitter is formed in the semiconductor material adjacent second portions of both the flat surface and the insulating material. A base separates the collector from the emitter.

Inventors

  • 👤 Richard D Schinella
  • 👤 Michael P Anthony

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 06:08
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/63; H10D84/01; H10D84/0112; H10D84/0114; H10D84/02; H10D84/03; H10D84/038; H10D99/00; H10P; H10P95/00; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/0121; H10W10/10; H10W10/13; H10W20/00; H10W20/20; Y; Y10; Y10S; Y10S148/00; Y10S148/085; Y10S148/096; Y10S148/106; Y10S148/117; Y10S148/167

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 379 words
A METHOD FOR FABRICATING A DOUBLE-DIFFUSED, LATERAL TRANSISTOR STRUCTURE COMPRISING THE STEPS OF: A. OXIDIZING A P-TYPE SILICON SUBSTRATE, B. FORMING AN OPENING IN THE SILICON DIOXIDE LAYER FORMED BY STEP (A) C. PREDEPOSITING AN N+-TYPE IMPURITY IN THE PORTION OF THE SUBSTRATE EXPOSED BY SAID OPENING AND HEATING SAID SUBSTRATE TO THERMALLY DRIVE SAID N+-TYPE IMPURITY INTO SAID SUBSTRATE TO FORM A BURIED LAYER, D. REMOVING THE REMAINING SILICON DIOXIDE FORMED BY STEP (A) FROM THE SURFACE OF SAID SUBSTRATE, E. EPITAXIALLY FORMING A LAYER OF P-TYPE CONDUCTIVITY ON SAID SUBSTRATE, F. FORMING A SELECTIVELY ETCHABLE MASK ON THE SURFACE OF SAID P-TYPE EPITAXIAL LAYER, G. REMOVING SAID MASK FROM SAID SURFACE OF SAID P-TYPE EPITAXIAL LAYER EXCEPT OVER A PORTION OF THE ACTIVE TRANSISTOR STRUCTURE TO BE FORMED, H. OXIDIZING THE SURFACE OF THE REMAINING EXPOSED EPITAXIAL LAYER TO FORM AN IMPURITY-DIFFUSION MASKING LAYER, I. DEFINING A BASE DIFFUSION OPENING IN THE SILICON DIOXIDE MATERIAL FORMED BY STEP (H), J. PREDEPOSITING AN N-TYPE IMPURITY IN SAID EPITAXIAL LAYER THROUGH SAID BASE DIFFUSION OPENING, K. REMOVING THE REMAINING SILICON DIOXIDE MATERIAL FORMED BY STEP (H), L. APPLYING A THERMAL OXIDATION MASKING MATERIAL OVER SAID ACTIVE TRANSISTOR STRUCTURE TO BE FORMED, M. ETCHING THE PORTION OF SAID EPITAXIAL LAYER NOT COVERED BY SAID THERMAL OXIDATION MASKING MATERIAL TO BE APPROXIMATELY ONE-HALF ITS DEPTH, N. HEATING SAID EPITAXIAL LAYER TO OXIDIZE SAID ETXHED PORTION OF SAID EPITAXIAL LAYER SO THAT THE SURFACE OF THE ISOLATIONFORMING, THERMALLY GROWN SILICON DIOXIDE CORRESPONDS APPROXIMATELY TO THE PLANE OF THE ORIGINAL SURFACE OF SAID EPITAXIAL LAYER AND SO THAT SAID PREDEPOSITED N-TYPE IMPURITIES DIFFUSE TO MEET SAID BURIED LAYER, O. REMOVING SAID THERMAL OXIDATION MASKING MATERIAL APPLIED BY STEP (1), P. REOXIDIZING SAID EPITAXIAL LAYER TO FORM A THIN PROTECTIVE SILICON DIOXIDE LAYER, Q. DEFINING SAID PROTECTIVE SILICON DIOXIDE LAYER FORMED BY STEPS (P) TO FORM EMITTER AND COLLECTOR CONTACT OPENINGS, R. PREDEPOSITING A P-TYPE IMPURITY IN SAID EPITAXIAL LAYER THROUGH SAID EMITTER AND COLLECTOR CONTACT OPENINGS AND HEATING SAID EPITAXIAL LAYER TO THERMALLY DRIVE SAID P-TYPE IMPURITIES INTO SAID EPITAXIAL LAYER TO FORM EMITTER AND COLLECTOR REGIONS, SAID EMITTER REGION STOPPING SHORT OF THE DIFFUSION FRONT ASSOCIATED WITH SAID BASE REGION, AND S. FORMING METAL CONTACT TO SAID EMITTER, BASE AND COLLECTOR REGIONS.
Claim 2
Independent Claim 379 words
A METHOD FOR FABRICATING A DOUBLE-DIFFUSED, LATERAL TRANSISTOR STRUCTURE COMPRISING THE STEPS OF: A. OXIDIZING A P-TYPE SILICON SUBSTRATE, B. FORMING AN OPENING IN THE SILICON DIOXIDE LAYER FORMED BY STEP (A) C. PREDEPOSITING AN N+-TYPE IMPURITY IN THE PORTION OF THE SUBSTRATE EXPOSED BY SAID OPENING AND HEATING SAID SUBSTRATE TO THERMALLY DRIVE SAID N+-TYPE IMPURITY INTO SAID SUBSTRATE TO FORM A BURIED LAYER, D. REMOVING THE REMAINING SILICON DIOXIDE FORMED BY STEP (A) FROM THE SURFACE OF SAID SUBSTRATE, E. EPITAXIALLY FORMING A LAYER OF P-TYPE CONDUCTIVITY ON SAID SUBSTRATE, F. FORMING A SELECTIVELY ETCHABLE MASK ON THE SURFACE OF SAID P-TYPE EPITAXIAL LAYER, G. REMOVING SAID MASK FROM SAID SURFACE OF SAID P-TYPE EPITAXIAL LAYER EXCEPT OVER A PORTION OF THE ACTIVE TRANSISTOR STRUCTURE TO BE FORMED, H. OXIDIZING THE SURFACE OF THE REMAINING EXPOSED EPITAXIAL LAYER TO FORM AN IMPURITY-DIFFUSION MASKING LAYER, I. DEFINING A BASE DIFFUSION OPENING IN THE SILICON DIOXIDE MATERIAL FORMED BY STEP (H), J. PREDEPOSITING AN N-TYPE IMPURITY IN SAID EPITAXIAL LAYER THROUGH SAID BASE DIFFUSION OPENING, K. REMOVING THE REMAINING SILICON DIOXIDE MATERIAL FORMED BY STEP (H), L. APPLYING A THERMAL OXIDATION MASKING MATERIAL OVER SAID ACTIVE TRANSISTOR STRUCTURE TO BE FORMED, M. ETCHING THE PORTION OF SAID EPITAXIAL LAYER NOT COVERED BY SAID THERMAL OXIDATION MASKING MATERIAL TO BE APPROXIMATELY ONE-HALF ITS DEPTH, N. HEATING SAID EPITAXIAL LAYER TO OXIDIZE SAID ETXHED PORTION OF SAID EPITAXIAL LAYER SO THAT THE SURFACE OF THE ISOLATIONFORMING, THERMALLY GROWN SILICON DIOXIDE CORRESPONDS APPROXIMATELY TO THE PLANE OF THE ORIGINAL SURFACE OF SAID EPITAXIAL LAYER AND SO THAT SAID PREDEPOSITED N-TYPE IMPURITIES DIFFUSE TO MEET SAID BURIED LAYER, O. REMOVING SAID THERMAL OXIDATION MASKING MATERIAL APPLIED BY STEP (1), P. REOXIDIZING SAID EPITAXIAL LAYER TO FORM A THIN PROTECTIVE SILICON DIOXIDE LAYER, Q. DEFINING SAID PROTECTIVE SILICON DIOXIDE LAYER FORMED BY STEPS (P) TO FORM EMITTER AND COLLECTOR CONTACT OPENINGS, R. PREDEPOSITING A P-TYPE IMPURITY IN SAID EPITAXIAL LAYER THROUGH SAID EMITTER AND COLLECTOR CONTACT OPENINGS AND HEATING SAID EPITAXIAL LAYER TO THERMALLY DRIVE SAID P-TYPE IMPURITIES INTO SAID EPITAXIAL LAYER TO FORM EMITTER AND COLLECTOR REGIONS, SAID EMITTER REGION STOPPING SHORT OF THE DIFFUSION FRONT ASSOCIATED WITH SAID BASE REGION, AND S. FORMING METAL CONTACT TO SAID EMITTER, BASE AND COLLECTOR REGIONS.
Claim 3
Dependent Claim 32 words
A method for fabricating a double-diffused, lateral transistor structure in accordance with claim 1 wherein step (f) comprises forming a silicon nitride passivation mask on the surface of said p-type epitaxial layer.
Claim 4
Dependent Claim 31 words
A method for fabricating a double-diffused, lateral transistor structure in accordance with claim 2 wherein step (1) comprises applying silicon nitride masking material over said active transistor structure to be formed.

References Cited (Backward Citations)

US3713008A Cited
US3473979A Cited
US3328214A Cited
US3411051A Cited
US3390025A Cited
US3397449A Cited
US3542551A Cited
US3623923A Cited
US3560278A Cited
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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1978-11-10 1979-05-12 1979-11-11 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1982-11-10 1983-05-12 1983-11-11 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1986-11-10 1987-05-12 1987-11-11 $7700.00 Window Closed / Lapsed

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