Patent US2076894A successfully refreshed from Google Patents.
Patent US6900122B2 successfully refreshed from Google Patents.
US6900122B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Low-temperature grown high-quality ultra-thin praseodymium gate dielectrics
Assignee: Micron Technology Inc
•
Filing: 2001-12-20
•
Granted: 2005-05-31
•
Expires: 2021-12-20
Abstract
Abstract A praseodymium (Pr) gate oxide and method of fabricating same that produces a high-quality and ultra-thin equivalent oxide thickness as compared to conventional SiO 2 gate oxides are provided. The Pr gate oxide is thermodynamically stable so that the oxide reacts minimally with a silicon substrate or other structures during any later high temperature processing stages. The process shown is performed at lower temperatures than the prior art, which further inhibits reactions with the silicon substrate or other structures. Using a thermal evaporation technique to deposit a Pr layer to be oxidized, the underlying substrate surface smoothness is preserved, thus providing improved and more consistent electrical properties in the resulting gate oxide.
Inventors
- 👤 Kie Y. Ahn
- 👤 Leonard Forbes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:11
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6302; H10P14/6304; H10P14/6314; C; C23; C23C; C23C14/00; C23C14/06; C23C14/14; C23C14/16; C23C14/58; C23C14/5826; C23C14/5846; C23C14/5853; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/0134; H10D64/01342; H10D64/60; H10D64/66; H10D64/68; H10D64/691; H10P14/40; H10P14/6319; H10P14/6322; H10P14/69; H10P14/692; H10P14/6938; H10P14/6939; H10P14/69396
Claims Analysis
Total Claims: 66
Claim 1
Independent Claim
46 words
A method of forming a gate oxide on a transistor body region, comprising: evaporation depositing a praseodymium (Pr) layer on the transistor body region; and oxidizing the Pr layer to form the gate oxide as a Pr 2 O 3 layer on the transistor body region.
Claim 2
Independent Claim
46 words
A method of forming a gate oxide on a transistor body region, comprising: evaporation depositing a praseodymium (Pr) layer on the transistor body region; and oxidizing the Pr layer to form the gate oxide as a Pr 2 O 3 layer on the transistor body region.
Claim 3
Dependent Claim
29 words
The method of claim 1 , wherein evaporation depositing the Pr layer includes evaporation depositing by electron beam evaporation to form the Pr layer as an amorphous Pr layer.
Claim 4
Dependent Claim
23 words
The method of claim 2 , wherein electron beam evaporation depositing the Pr layer includes electron beam evaporating a 99.9999% pure Pr target.
Claim 5
Dependent Claim
24 words
The method of claim 1 , wherein evaporation depositing the Pr layer includes evaporation depositing at an approximate substrate temperature range of 150-400° C.
Claim 6
Dependent Claim
20 words
The method of claim 1 , wherein oxidizing the Pr layer includes oxidizing at a temperature of approximately 400° C.
Claim 7
Dependent Claim
16 words
The method of claim 1 , wherein oxidizing the Pr layer includes oxidizing with atomic oxygen.
Claim 8
Dependent Claim
34 words
The method of claim 1 , wherein oxidizing the Pr layer includes oxidizing using a krypton (Kr)/oxygen (O 2 ) mixed plasma process having a plasma density above about 10 12 /cm 3 .
Claim 9
Dependent Claim
29 words
The method of claim 1 , wherein the method includes forming the Pr 2 O 3 layer to have an equivalent oxide thickness (EOT) of less than 2 nm.
Claim 10
Independent Claim
58 words
A method of forming a gate oxide on a transistor body region, comprising: evaporation depositing a praseodymium (Pr) layer on the transistor body region; and oxidizing the Pr layer using a krypton (Kr)/oxygen (O 2 ) mixed plasma process to form the gate oxide as an oxide layer of Pr 2 O 3 on the transistor body region.
Claim 11
Independent Claim
58 words
A method of forming a gate oxide on a transistor body region, comprising: evaporation depositing a praseodymium (Pr) layer on the transistor body region; and oxidizing the Pr layer using a krypton (Kr)/oxygen (O 2 ) mixed plasma process to form the gate oxide as an oxide layer of Pr 2 O 3 on the transistor body region.
Claim 12
Dependent Claim
19 words
The method of claim 9 , wherein evaporation depositing the metal layer includes evaporation depositing by electron beam evaporation.
Claim 13
Dependent Claim
23 words
The method of claim 10 , wherein electron beam evaporation depositing the Pr layer includes electron beam evaporating a 99.9999% pure Pr target.
Claim 14
Dependent Claim
24 words
The method of claim 9 , wherein evaporation depositing the Pr layer includes evaporation depositing at an approximate substrate temperature range of 150-400° C.
Claim 15
Independent Claim
50 words
A method of forming a gate oxide on a transistor body region, comprising: electron beam evaporation depositing a layer of praseodymium (Pr) on the transistor body region; and oxidizing the Pr layer to form the gate oxide as a Pr 2 O 3 oxide layer on the transistor body region.
Claim 16
Independent Claim
50 words
A method of forming a gate oxide on a transistor body region, comprising: electron beam evaporation depositing a layer of praseodymium (Pr) on the transistor body region; and oxidizing the Pr layer to form the gate oxide as a Pr 2 O 3 oxide layer on the transistor body region.
Claim 17
Dependent Claim
31 words
The method of claim 13 , wherein the method includes oxidizing the Pr layer to form the Pr 2 O 3 oxide to have a thickness of 2 nm or less.
Claim 18
Dependent Claim
21 words
The method of claim 13 , wherein the method includes annealing the Pr 2 O 3 oxide layer at 600° C.
Claim 19
Independent Claim
48 words
A method of forming a gate oxide on a transistor body region, comprising: evaporation depositing a praseodymium (Pr) layer on the transistor body region; oxidizing the Pr layer to form the gate oxide as a Pr 2 O 3 layer; and annealing the Pr 2 O 3 layer.
Claim 20
Independent Claim
48 words
A method of forming a gate oxide on a transistor body region, comprising: evaporation depositing a praseodymium (Pr) layer on the transistor body region; oxidizing the Pr layer to form the gate oxide as a Pr 2 O 3 layer; and annealing the Pr 2 O 3 layer.
Claim 21
Dependent Claim
30 words
The method of claim 16 , wherein the method further includes annealing the Pr 2 O 3 layer such that the Pr 2 O 3 layer is amorphous after annealing.
Claim 22
Dependent Claim
22 words
The method of claim 16 , wherein the method further includes evaporation depositing the Pr layer from a 99.9999% pure Pr source.
Claim 23
Dependent Claim
27 words
The method of claim 16 , wherein the method further includes evaporation depositing the Pr layer at temperatures ranging from about 150° C. to about 400° C.
Claim 24
Independent Claim
61 words
A method of forming a gate oxide on a transistor body region, comprising: evaporation depositing a praseodymium (Pr) layer on the transistor body region; and oxidizing the Pr layer using a krypton (Kr)/oxygen (O 2 ) mixed plasma process to form the gate oxide as a Pr 2 O 3 layer using an ion bombardment energy less than about 7 eV.
Claim 25
Independent Claim
61 words
A method of forming a gate oxide on a transistor body region, comprising: evaporation depositing a praseodymium (Pr) layer on the transistor body region; and oxidizing the Pr layer using a krypton (Kr)/oxygen (O 2 ) mixed plasma process to form the gate oxide as a Pr 2 O 3 layer using an ion bombardment energy less than about 7 eV.
Claim 26
Dependent Claim
30 words
The method of claim 19 , wherein the method further includes conducting the Kr/O 2 mixed plasma process at temperatures to inhibit reactions with material forming the transistor body region.
Claim 27
Dependent Claim
22 words
The method of claim 19 , wherein the method further includes conducting the Kr/O 2 mixed plasma process at about 400° C.
Claim 28
Dependent Claim
33 words
The method of claim 19 , wherein the method further includes evaporation depositing the Pr layer with the transistor body region at a temperature ranging from about 150° C. to about 400° C.
Claim 29
Independent Claim
58 words
A method of forming a gate oxide on a transistor body region, comprising: electron beam evaporation depositing a layer of praseodymium (Pr) on the transistor body region, the body region at a temperature ranging from about 150° C. to about 400° C.; oxidizing the Pr layer to form the gate oxide as a Pr 2 O 3 layer.
Claim 30
Independent Claim
58 words
A method of forming a gate oxide on a transistor body region, comprising: electron beam evaporation depositing a layer of praseodymium (Pr) on the transistor body region, the body region at a temperature ranging from about 150° C. to about 400° C.; oxidizing the Pr layer to form the gate oxide as a Pr 2 O 3 layer.
Claim 31
Dependent Claim
30 words
The method of claim 24 , wherein the method further includes annealing the Pr 2 O 3 layer such that the Pr 2 O 3 layer is amorphous after annealing.
Claim 32
Dependent Claim
22 words
The method of claim 24 , wherein the method further includes evaporation depositing the Pr layer from a 99.9999% pure Pr source.
Claim 33
Independent Claim
68 words
A method of forming a gate oxide on a transistor body region, comprising: electron beam evaporation depositing a layer of praseodymium (Pr) on the transistor body region; and oxidizing the Pr layer by a krypton(Kr)/oxygen (O 2 ) mixed plasma process using a krypton(Kr)/oxygen (O 2 ) mixed gas that is about 3% oxygen to form the gate oxide as a layer of Pr 2 O 3 .
Claim 34
Independent Claim
68 words
A method of forming a gate oxide on a transistor body region, comprising: electron beam evaporation depositing a layer of praseodymium (Pr) on the transistor body region; and oxidizing the Pr layer by a krypton(Kr)/oxygen (O 2 ) mixed plasma process using a krypton(Kr)/oxygen (O 2 ) mixed gas that is about 3% oxygen to form the gate oxide as a layer of Pr 2 O 3 .
Claim 35
Dependent Claim
30 words
The method of claim 27 , wherein the method further includes conducting the Kr/O 2 mixed plasma process at temperatures to inhibit reactions with material forming the transistor body region.
Claim 36
Dependent Claim
29 words
The method of claim 27 , wherein the method further includes conducting the Kr/O 2 mixed plasma process using a microwave power density of about 5 W/cm 2 .
Claim 37
Independent Claim
75 words
A method of forming a gate oxide on a transistor body region, comprising: electron beam evaporation depositing a layer of praseodymium (Pr) on the body region; oxidizing the Pr layer by a krypton(Kr)/oxygen (O 2 ) mixed plasma process to form the gate oxide as a layer of Pr 2 O 3 ; and conducting the electron beam evaporation and oxidizing the Pr layer at temperatures to inhibit reactions with material forming the body region.
Claim 38
Independent Claim
75 words
A method of forming a gate oxide on a transistor body region, comprising: electron beam evaporation depositing a layer of praseodymium (Pr) on the body region; oxidizing the Pr layer by a krypton(Kr)/oxygen (O 2 ) mixed plasma process to form the gate oxide as a layer of Pr 2 O 3 ; and conducting the electron beam evaporation and oxidizing the Pr layer at temperatures to inhibit reactions with material forming the body region.
Claim 39
Dependent Claim
30 words
The method of claim 30 , wherein the method further includes annealing the Pr 2 O 3 layer such that the Pr 2 O 3 layer is amorphous after annealing.
Claim 40
Dependent Claim
23 words
The method of claim 30 , wherein the method further includes evaporation depositing the praseodymium (Pr) layer from a 99.9999% pure Pr source.
Claim 41
Dependent Claim
30 words
The method of claim 30 , wherein the method further includes oxidizing the Pr layer to form the Pr 2 O 3 at a growth rate of about 1.5 nm/min.
Claim 42
Dependent Claim
21 words
The method of claim 30 , wherein the method further includes forming the gate oxide on a silicon transistor body region.
Claim 43
Independent Claim
68 words
A method of forming a transistor, comprising: forming first and second source/drain regions; forming a transistor body region between the first and second source/drain regions; evaporation depositing a praseodymium (Pr) layer on the transistor body region; oxidizing the Pr layer to form a gate oxide as a Pr 2 O 3 layer on the transistor body region; and coupling a gate to the Pr 2 O 3 layer.
Claim 44
Independent Claim
68 words
A method of forming a transistor, comprising: forming first and second source/drain regions; forming a transistor body region between the first and second source/drain regions; evaporation depositing a praseodymium (Pr) layer on the transistor body region; oxidizing the Pr layer to form a gate oxide as a Pr 2 O 3 layer on the transistor body region; and coupling a gate to the Pr 2 O 3 layer.
Claim 45
Dependent Claim
29 words
The method of claim 35 , wherein evaporation depositing the Pr layer includes evaporation depositing by electron beam evaporation to form the Pr layer as an amorphous Pr layer.
Claim 46
Dependent Claim
23 words
The method of claim 36 , wherein electron beam evaporation depositing the Pr layer includes electron beam evaporating a 99.9999% pure Pr target.
Claim 47
Dependent Claim
24 words
The method of claim 35 , wherein evaporation depositing the Pr layer includes evaporation depositing at an approximate substrate temperature range of 150-400° C.
Claim 48
Dependent Claim
20 words
The method of claim 35 , wherein oxidizing the Pr layer includes oxidizing at a temperature of approximately 400° C.
Claim 49
Dependent Claim
16 words
The method of claim 35 , wherein oxidizing the Pr layer includes oxidizing with atomic oxygen.
Claim 50
Dependent Claim
23 words
The method of claim 35 , wherein oxidizing the Pr layer includes oxidizing using a krypton (Kr)/oxygen (O 2 ) mixed plasma process.
Claim 51
Independent Claim
134 words
A method of forming a memory array, comprising: forming a number of access transistors, comprising: forming first and second source/drain regions; forming a transistor body region between the first and second source/drain regions; evaporation depositing a praseodymium (Pr) layer on the transistor body region; oxidizing the Pr layer to form a gate oxide as a Pr 2 O 3 layer on the transistor body region; coupling a gate to the Pr 2 O 3 layer; forming a number of wordlines coupled to a number of the gates of the number of access transistors; forming a number of sourcelines coupled to a number of the first source/drain regions of the number of access transistors; and forming a number of bitlines coupled to a number of the second source/drain regions of the number of access transistors.
Claim 52
Independent Claim
134 words
A method of forming a memory array, comprising: forming a number of access transistors, comprising: forming first and second source/drain regions; forming a transistor body region between the first and second source/drain regions; evaporation depositing a praseodymium (Pr) layer on the transistor body region; oxidizing the Pr layer to form a gate oxide as a Pr 2 O 3 layer on the transistor body region; coupling a gate to the Pr 2 O 3 layer; forming a number of wordlines coupled to a number of the gates of the number of access transistors; forming a number of sourcelines coupled to a number of the first source/drain regions of the number of access transistors; and forming a number of bitlines coupled to a number of the second source/drain regions of the number of access transistors.
Claim 53
Dependent Claim
29 words
The method of claim 42 , wherein evaporation depositing the Pr layer includes evaporation depositing by electron beam evaporation to form the Pr layer as an amorphous Pr layer.
Claim 54
Dependent Claim
23 words
The method of claim 43 , wherein electron beam evaporation depositing the Pr layer includes electron beam evaporating a 99.9999% pure Pr target.
Claim 55
Dependent Claim
24 words
The method of claim 42 , wherein evaporation depositing the Pr layer includes evaporation depositing at an approximate substrate temperature range of 150-400° C.
Claim 56
Dependent Claim
20 words
The method of claim 42 , wherein oxidizing the Pr layer includes oxidizing at a temperature of approximately 400° C.
Claim 57
Dependent Claim
16 words
The method of claim 42 , wherein oxidizing the Pr layer includes oxidizing with atomic oxygen.
Claim 58
Dependent Claim
23 words
The method of claim 42 , wherein oxidizing the Pr layer includes oxidizing using a krypton (Kr)/oxygen (O 2 ) mixed plasma process.
Claim 59
Independent Claim
155 words
A method of forming an information handling system, comprising: forming a processor; forming a memory array, comprising: forming a number of access transistors, comprising: forming first and second source/drain regions; forming a transistor body region between the first and second source/drain regions; evaporation depositing a praseodymium (Pr) layer on the transistor body region; oxidizing the Pr layer to form a gate oxide as a Pr 2 O 3 layer on the transistor body region; coupling a gate to the Pr 2 O 3 layer; forming a number of wordlines coupled to a number of the gates of the number of access transistors; forming a number of sourcelines coupled to a number of the first source/drain regions of the number of access transistors; forming a number of bitlines coupled to a number of the second source/drain regions of the number of access transistors; and forming a system bus that couples the processor to the memory array.
Claim 60
Independent Claim
155 words
A method of forming an information handling system, comprising: forming a processor; forming a memory array, comprising: forming a number of access transistors, comprising: forming first and second source/drain regions; forming a transistor body region between the first and second source/drain regions; evaporation depositing a praseodymium (Pr) layer on the transistor body region; oxidizing the Pr layer to form a gate oxide as a Pr 2 O 3 layer on the transistor body region; coupling a gate to the Pr 2 O 3 layer; forming a number of wordlines coupled to a number of the gates of the number of access transistors; forming a number of sourcelines coupled to a number of the first source/drain regions of the number of access transistors; forming a number of bitlines coupled to a number of the second source/drain regions of the number of access transistors; and forming a system bus that couples the processor to the memory array.
Claim 61
Dependent Claim
29 words
The method of claim 49 , wherein evaporation depositing the Pr layer includes evaporation depositing by electron beam evaporation to form the Pr layer as an amorphous Pr layer.
Claim 62
Dependent Claim
24 words
The method of claim 50 , wherein electron beam evaporation depositing the Pr layer includes electron beam evaporation of a 99.9999% pure Pr target.
Claim 63
Dependent Claim
24 words
The method of claim 49 , wherein evaporation depositing the Pr layer includes evaporation depositing at an approximate substrate temperature range of 150-400° C.
Claim 64
Dependent Claim
20 words
The method of claim 49 , wherein oxidizing the Pr layer includes oxidizing at a temperature of approximately 400° C.
Claim 65
Dependent Claim
16 words
The method of claim 49 , wherein oxidizing the Pr layer includes oxidizing with atomic oxygen.
Claim 66
Dependent Claim
23 words
The method of claim 49 , wherein oxidizing the Pr layer includes oxidizing using a krypton (Kr)/oxygen (O 2 ) mixed plasma process.
References Cited (Backward Citations)
US4058430A
Cited
US4215156A
Cited
US4333808A
Cited
US4399424A
Cited
US4647947A
Cited
US4920071A
Cited
US4767641A
Cited
US5840897A
Cited
US5810923A
Cited
US5828080A
Cited
US5822256A
Cited
US5801105A
Cited
US5795808A
Cited
US6387712B1
Cited
US5698022A
Cited
US6368398B2
Cited
US6010969A
Cited
US6203726B1
Cited
US6013553A
Cited
US6020024A
Cited
US6225168B1
Cited
US6027961A
Cited
US6391769B1
Cited
US6225237B1
Cited
US6211035B1
Cited
US6171900B1
Cited
US6273951B1
Cited
US6297539B1
Cited
US6458701B1
Cited
US6303481B2
Cited
US6527866B1
Cited
US6521911B2
Cited
US6465334B1
Cited
US6660660B2
Cited
US6368941B1
Cited
US20020089023A1
Cited
US6713846B1
Cited
US6495436B2
Cited
US6448192B1
Cited
US20020155689A1
Cited
US6514828B2
Cited
US20020155688A1
Cited
US20020192974A1
Cited
US20030017717A1
Cited
US6534420B2
Cited
US6730575B2
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2008-05-30 | 2008-11-29 | 2009-05-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2012-05-30 | 2012-11-29 | 2013-05-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2016-05-30 | 2016-11-29 | 2017-05-31 | $7700.00 | Window Closed / Lapsed |