Patent US6857064B2 successfully refreshed from Google Patents.
US6857064B2
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Method and apparatus for processing events in a multithreaded processor
Assignee: Intel Corp
•
Filing: 2001-11-30
•
Granted: 2005-02-15
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Expires: 2021-11-30
Abstract
Abstract In a multithreaded processor, events are categorized according to which of a “soft” state clearing (“nuke”) process and a “hard” nuke process should be performed in response to each event. When an event is detected for a thread, either the soft nuke or hard nuke process is executed, according to the type of event, prior to invoking an event handler. The soft nuke process performs less than all of the actions performed by the hard nuke process and requires much less time to execute. If multiple threads are being processed, the hard nuke process requires synchronization between the threads and clears state for each thread, whereas the soft nuke process does not require cross-thread synchronization and clears state only for the thread in which the event was detected. In one embodiment, the soft nuke process is implemented in microcode, while the hard nuke process is hardware-implemented.
Inventors
- 👤 Lawrence O. Smith
- 👤 S. Dion Rodgers
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 16:08
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30076; G06F9/3009; G06F9/30181; G06F9/30185; G06F9/38; G06F9/3836; G06F9/3851; G06F9/3854; G06F9/3861; G06F9/3885; G06F9/3888
Claims Analysis
Total Claims: 66
Claim 1
Independent Claim
83 words
A processor comprising: retirement logic from which microinstructions for both a first thread and a second thread being processed within the processor are retired; and an event detector, coupled to the retirement logic, to detect an event for the first thread; responsive to the detection of the event, to determine whether to execute a first state clearing process or a second state clearing process; and to execute either the first state clearing process or the second state clearing process, depending on the event.
Claim 2
Dependent Claim
83 words
A processor comprising: retirement logic from which microinstructions for both a first thread and a second thread being processed within the processor are retired; and an event detector, coupled to the retirement logic, to detect an event for the first thread; responsive to the detection of the event, to determine whether to execute a first state clearing process or a second state clearing process; and to execute either the first state clearing process or the second state clearing process, depending on the event.
Claim 3
Dependent Claim
39 words
A processor as recited in claim 1 , wherein the second state clearing process requires synchronization between the first and second threads, and wherein the first state clearing process does not require synchronization between the first and second threads.
Claim 4
Dependent Claim
44 words
A processor as recited in claim 1 , wherein the first state clearing process clears state for only one of the first thread and the second thread, and the second state clearing process clears state for both the first thread and the second thread.
Claim 5
Dependent Claim
47 words
A processor as recited in claim 1 , wherein the first state clearing process includes a first plurality of actions and the second state clearing process includes a second plurality of actions, the first plurality of actions being a partial subset of the second plurality of actions.
Claim 6
Dependent Claim
26 words
A processor as recited in claim 4 , wherein the first state clearing process requires substantially less time to execute than the second state clearing process.
Claim 7
Dependent Claim
29 words
A processor as recited in claim 1 , wherein the first state clearing process comprises clearing state for the first thread and not clearing state for the second thread.
Claim 8
Dependent Claim
52 words
A processor as recited in claim 6 , wherein the second state clearing process comprises: monitoring the second thread to detect a clearing point for the second thread; and in response to detection of the clearing point for the second thread, clearing state for both the first thread and the second thread.
Claim 9
Dependent Claim
30 words
A processor as recited in claim 1 , wherein the first state clearing process is executed if the event is one of a predetermined set of memory ordering conflict events.
Claim 10
Dependent Claim
21 words
A processor as recited in claim 8 , wherein the predetermined set of memory ordering conflict events comprises a multithreaded snoop.
Claim 11
Dependent Claim
22 words
A processor as recited in claim 8 , wherein the predetermined set of memory ordering conflict events comprises an external processor snoop.
Claim 12
Dependent Claim
22 words
A processor as recited in claim 8 , wherein the predetermined set of memory ordering conflict events comprises a memory alias event.
Claim 13
Dependent Claim
45 words
A processor as recited in claim 1 , wherein the second state clearing process is identical for each event in response to which it is used, and wherein the first state clearing process varies according to the event in response to which it is used.
Claim 14
Dependent Claim
56 words
A processor as recited in claim 12 , wherein the multithreaded processor comprises a store buffer to buffer store operations, wherein the second state clearing process comprises clearing the store buffer, and wherein the first state clearing process comprises clearing the store buffer only in response to certain events and not in response to other events.
Claim 15
Dependent Claim
25 words
A processor as recited in claim 1 , wherein the first state clearing process is software-implemented and the second state clearing process is hardware implemented.
Claim 16
Dependent Claim
33 words
A processor as recited in claim 1 , wherein the first state clearing process and the second state clearing process each comprise clearing the state of an instruction pipeline of the multithreaded processor.
Claim 17
Dependent Claim
127 words
A microprocessor comprising: means for detecting an event for a first thread being processed in the microprocessor, the microprocessor also having a second thread being processed concurrently with the first thread; means for determining, in response to detecting the event, whether a first state clearing process is to be used responsive to the event; and means for executing the first state clearing process if the first state clearing process is to be used responsive to the event, the first state clearing process clearing state for only the first thread, and for executing the second state clearing process if the second state clearing process is to be used responsive to the event, the second state clearing process clearing state for both the first thread and the second thread.
Claim 18
Dependent Claim
127 words
A microprocessor comprising: means for detecting an event for a first thread being processed in the microprocessor, the microprocessor also having a second thread being processed concurrently with the first thread; means for determining, in response to detecting the event, whether a first state clearing process is to be used responsive to the event; and means for executing the first state clearing process if the first state clearing process is to be used responsive to the event, the first state clearing process clearing state for only the first thread, and for executing the second state clearing process if the second state clearing process is to be used responsive to the event, the second state clearing process clearing state for both the first thread and the second thread.
Claim 19
Dependent Claim
39 words
A microprocessor as recited in claim 16 , wherein the second state clearing process requires synchronization between the first and second threads, and wherein the first state clearing process does not require synchronization between the first and second threads.
Claim 20
Dependent Claim
26 words
A microprocessor as recited in claim 16 , wherein the first state clearing process comprises clearing state for the first thread independently of the second thread.
Claim 21
Dependent Claim
52 words
A microprocessor as recited in claim 18 , wherein the second state clearing process comprises: monitoring the second thread to detect a clearing point for the second thread; and in response to detection of the clearing point for the second thread, clearing state for both the first thread and the second thread.
Claim 22
Dependent Claim
46 words
A microprocessor as recited in claim 16 , further comprising categorizing a plurality of events which may occur in the multithreaded processor according to which of the first state clearing process and the second state clearing process is to be performed in response to each event.
Claim 23
Dependent Claim
47 words
A microprocessor as recited in claim 16 , wherein the first state clearing process includes a first plurality of actions and the second state clearing process includes a second plurality of actions, the first plurality of actions being a partial subset of the second plurality of actions.
Claim 24
Dependent Claim
26 words
A microprocessor as recited in claim 16 , wherein the first state clearing process requires substantially less time to execute than the second state clearing process.
Claim 25
Dependent Claim
24 words
A microprocessor as recited in claim 16 , wherein the first state clearing process is software-implemented and the second state clearing process is hardware-implemented.
Claim 26
Dependent Claim
30 words
A microprocessor as recited in claim 16 , wherein the first state clearing process is executed if the event is one of a predetermined set of memory ordering conflict events.
Claim 27
Dependent Claim
21 words
A microprocessor as recited in claim 24 , wherein the predetermined set of memory ordering conflict events comprises a multithreaded snoop.
Claim 28
Dependent Claim
22 words
A microprocessor as recited in claim 24 , wherein the predetermined set of memory ordering conflict events comprises an external processor snoop.
Claim 29
Dependent Claim
22 words
A microprocessor as recited in claim 24 , wherein the predetermined set of memory ordering conflict events comprises a memory alias event.
Claim 30
Dependent Claim
45 words
A microprocessor as recited in claim 16 , wherein the second state clearing process is identical for each event in response to which it is used, and wherein the first state clearing process varies according to the event in response to which it is used.
Claim 31
Dependent Claim
56 words
A microprocessor as recited in claim 28 , wherein the multithreaded processor comprises a store buffer to buffer store operations, wherein the second state clearing process comprises clearing the store buffer, and wherein the first state clearing process comprises clearing the store buffer only in response to certain events and not in response to other events.
Claim 32
Dependent Claim
33 words
A microprocessor as recited in claim 16 , wherein the first state clearing process and the second state clearing process each comprise clearing the state of an instruction pipeline of the multithreaded processor.
Claim 33
Dependent Claim
147 words
A machine-readable storage medium storing instructions which, when executed by a multithreaded processor, cause the processor to perform a method comprising: detecting an event for a first thread being processed in the multithreaded processor, the multithreaded processor also having a second thread being processed concurrently with the first thread; in response to detecting the event, determining whether a first state clearing process is to be used responsive to the event; if the first state clearing process is to be used responsive to the event, then executing the first state clearing process, the first state clearing process clearing state for only the first thread; and if the first state clearing process is not to be used responsive to the event occurrence, then executing a second state clearing process responsive to the event, the second state clearing process clearing state for both the first thread and the second thread.
Claim 34
Dependent Claim
147 words
A machine-readable storage medium storing instructions which, when executed by a multithreaded processor, cause the processor to perform a method comprising: detecting an event for a first thread being processed in the multithreaded processor, the multithreaded processor also having a second thread being processed concurrently with the first thread; in response to detecting the event, determining whether a first state clearing process is to be used responsive to the event; if the first state clearing process is to be used responsive to the event, then executing the first state clearing process, the first state clearing process clearing state for only the first thread; and if the first state clearing process is not to be used responsive to the event occurrence, then executing a second state clearing process responsive to the event, the second state clearing process clearing state for both the first thread and the second thread.
Claim 35
Dependent Claim
41 words
A machine-readable storage medium as recited in claim 31 , wherein the second state clearing process requires synchronization between the first and second threads, and wherein the first state clearing process does not require synchronization between the first and second threads.
Claim 36
Dependent Claim
28 words
A machine-readable storage medium as recited in claim 32 , wherein the first state clearing process comprises clearing state for the first thread independently of the second thread.
Claim 37
Dependent Claim
54 words
A machine-readable storage medium as recited in claim 31 , wherein the second state clearing process comprises: monitoring the second thread to detect a clearing point for the second thread; and in response to detection of the clearing point for the second thread, clearing state for both the first thread and the second thread.
Claim 38
Dependent Claim
48 words
A machine-readable storage medium as recited in claim 31 , further comprising categorizing a plurality of events which may occur in the multithreaded processor according to which of the first state clearing process and the second state clearing process is to be performed in response to each event.
Claim 39
Dependent Claim
49 words
A machine-readable storage medium as recited in claim 31 , wherein the first state clearing process includes a first plurality of actions and the second state clearing process includes a second plurality of actions, the first plurality of actions being a partial subset of the second plurality of actions.
Claim 40
Dependent Claim
28 words
A machine-readable storage medium as recited in claim 31 , wherein the first state clearing process requires substantially less time to execute than the second state clearing process.
Claim 41
Dependent Claim
26 words
A machine-readable storage medium as recited in claim 31 , wherein the first state clearing process is software-implemented and the second state clearing process is hardware-implemented.
Claim 42
Dependent Claim
32 words
A machine-readable storage medium as recited in claim 31 , wherein the first state clearing process is executed if the event is one of a predetermined set of memory ordering conflict events.
Claim 43
Dependent Claim
23 words
A machine-readable storage medium as recited in claim 39 , wherein the predetermined set of memory ordering conflict events comprises a multithreaded snoop.
Claim 44
Dependent Claim
24 words
A machine-readable storage medium as recited in claim 39 , wherein the predetermined set of memory ordering conflict events comprises an external processor snoop.
Claim 45
Dependent Claim
24 words
A machine-readable storage medium as recited in claim 39 , wherein the predetermined set of memory ordering conflict events comprises a memory alias event.
Claim 46
Dependent Claim
47 words
A machine-readable storage medium as recited in claim 31 , wherein the second state clearing process is identical for each event in response to which it is used, and wherein the first state clearing process varies according to the event in response to which it is used.
Claim 47
Dependent Claim
59 words
A machine-readable storage medium as recited in claim 43 , wherein the multithreaded processor comprises a store buffer to buffer store operations, where in the second state clearing process comprises clearing the store buffer, and wherein the first state clearing process comprises clearing the store buffer only in response to certain events and not in response to other events.
Claim 48
Dependent Claim
35 words
A machine-readable storage medium as recited in claim 31 , wherein the first state clearing process and the second state clearing process each comprise clearing the state of an instruction pipeline of the multithreaded processor.
Claim 49
Independent Claim
143 words
A method comprising: categorizing a plurality of events that can occur in a multithreaded processor according to which of a plurality of state clearing processes is to be performed in response to each event, the plurality of state clearing processes including a first state clearing process and a second state clearing process, the first state clearing process to clear state for only one of a plurality of threads being processing concurrently in the processor, the second state clearing process to clear state for at least two of said plurality of threads; in response to detecting an event in the processor, determining whether to execute the first state clearing process or the second state clearing process, according to a type of the event; and executing either the first state clearing process or the second state clearing process, according to the outcome of said determining.
Claim 50
Independent Claim
143 words
A method comprising: categorizing a plurality of events that can occur in a multithreaded processor according to which of a plurality of state clearing processes is to be performed in response to each event, the plurality of state clearing processes including a first state clearing process and a second state clearing process, the first state clearing process to clear state for only one of a plurality of threads being processing concurrently in the processor, the second state clearing process to clear state for at least two of said plurality of threads; in response to detecting an event in the processor, determining whether to execute the first state clearing process or the second state clearing process, according to a type of the event; and executing either the first state clearing process or the second state clearing process, according to the outcome of said determining.
Claim 51
Dependent Claim
47 words
A method as recited in claim 46 , wherein the first state clearing process includes a first plurality of actions and the second state clearing process includes a second plurality of actions, the first plurality of actions being a partial subset of the second plurality of actions.
Claim 52
Dependent Claim
26 words
A method as recited in claim 47 , wherein the first state clearing process requires substantially less time to execute than the second state clearing process.
Claim 53
Dependent Claim
26 words
A method as recited in claim 46 , wherein the first state clearing process comprises clearing state for the first thread independently of the second thread.
Claim 54
Dependent Claim
52 words
A method as recited in claim 49 , wherein the second state clearing process comprises: monitoring the second thread to detect a clearing point for the second thread; and in response to detection of the clearing point for the second thread, clearing state for both the first thread and the second thread.
Claim 55
Dependent Claim
30 words
A method as recited in claim 46 , wherein the first state clearing process is executed if the event is one of a predetermined set of memory ordering conflict events.
Claim 56
Dependent Claim
21 words
A method as recited in claim 51 , wherein the predetermined set of memory ordering conflict events comprises a multithreaded snoop.
Claim 57
Dependent Claim
22 words
A method as recited in claim 51 , wherein the predetermined set of memory ordering conflict events comprises an external processor snoop.
Claim 58
Dependent Claim
22 words
A method as recited in claim 51 , wherein the predetermined set of memory ordering conflict events comprises a memory alias event.
Claim 59
Dependent Claim
45 words
A method as recited in claim 46 , wherein the second state clearing process is identical for each event in response to which it is used, and wherein the first state clearing process varies according to the event in response to which it is used.
Claim 60
Dependent Claim
56 words
A method as recited in claim 46 , wherein the multithreaded processor comprises a store buffer to buffer store operations, wherein the second state clearing process comprises clearing the store buffer, and wherein the first state clearing process comprises clearing the store buffer only in response to certain events and not in response to other events.
Claim 61
Dependent Claim
25 words
A method as recited in claim 46 , wherein the first state clearing process is software-implemented and the second state clearing process is hardware implemented.
Claim 62
Dependent Claim
33 words
A method as recited in claim 46 , wherein the first state clearing process and the second state clearing process each comprise clearing the state of an instruction pipeline of the multithreaded processor.
Claim 63
Independent Claim
317 words
A method comprising: categorizing a plurality of events which may occur in a multithreaded processor according to which of a plurality of state clearing processes can be performed in response to each event, each of the plurality of state clearing processes capable of execution in the multithreaded processor, the plurality of state clearing processes including a software-implemented state clearing process and a hardware-implemented state clearing process, the software-implemented state clearing process including a first plurality of actions and the hardware implemented state clearing process including a second plurality of actions, the first plurality of actions being a partial subset of the second plurality of actions, wherein the software-implemented state clearing process requires substantially less time to execute than the hardware-implemented state clearing process; detecting an event for a first thread being processed in the multithreaded processor, the multithreaded processor also having a second thread being processed concurrently with the first thread; in response to detecting the event, determining whether the software implemented state clearing process can be used responsive to the event; if the software-implemented state clearing process can be used responsive to the event, then executing the software-implemented state clearing process, including clearing state in the multithreaded processor for the first thread but not the second thread, wherein said clearing state for the first thread is done independently of the second thread; if the software-implemented state clearing process cannot be used responsive to the event occurrence, then executing the hardware-implemented state clearing process responsive to the event, the hardware-implemented state clearing process including monitoring the second thread to detect a clearing point for the second thread, and in response to detection of the clearing point for the second thread, clearing state within the multithreaded processor for both the first thread and the second thread; and invoking an event handler to service the event after executing the software-implemented state clearing process or the hardware-implemented state clearing process.
Claim 64
Independent Claim
317 words
A method comprising: categorizing a plurality of events which may occur in a multithreaded processor according to which of a plurality of state clearing processes can be performed in response to each event, each of the plurality of state clearing processes capable of execution in the multithreaded processor, the plurality of state clearing processes including a software-implemented state clearing process and a hardware-implemented state clearing process, the software-implemented state clearing process including a first plurality of actions and the hardware implemented state clearing process including a second plurality of actions, the first plurality of actions being a partial subset of the second plurality of actions, wherein the software-implemented state clearing process requires substantially less time to execute than the hardware-implemented state clearing process; detecting an event for a first thread being processed in the multithreaded processor, the multithreaded processor also having a second thread being processed concurrently with the first thread; in response to detecting the event, determining whether the software implemented state clearing process can be used responsive to the event; if the software-implemented state clearing process can be used responsive to the event, then executing the software-implemented state clearing process, including clearing state in the multithreaded processor for the first thread but not the second thread, wherein said clearing state for the first thread is done independently of the second thread; if the software-implemented state clearing process cannot be used responsive to the event occurrence, then executing the hardware-implemented state clearing process responsive to the event, the hardware-implemented state clearing process including monitoring the second thread to detect a clearing point for the second thread, and in response to detection of the clearing point for the second thread, clearing state within the multithreaded processor for both the first thread and the second thread; and invoking an event handler to service the event after executing the software-implemented state clearing process or the hardware-implemented state clearing process.
Claim 65
Dependent Claim
39 words
A method as recited in claim 59 , wherein the hardware-implemented state clearing process requires synchronization between the first and second threads, and wherein the software-implemented state clearing process does not require synchronization between the first and second threads.
Claim 66
Dependent Claim
30 words
A method as recited in claim 46 , wherein the software-implemented state clearing process is executed if the event is one of a predetermined set of memory ordering conflict events.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2008-02-15 | 2008-08-16 | 2009-02-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2012-02-15 | 2012-08-16 | 2013-02-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2016-02-15 | 2016-08-16 | 2017-02-15 | $7700.00 | Window Closed / Lapsed |