US5809271A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for changing flow of control in a processor
Assignee: Intel Corp
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Filing: 1995-08-23
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Granted: 1998-09-15
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Expires: 2015-08-23
Abstract
Abstract A simplified method and apparatus for handling the change of instruction control flow in a microprocessor is provided. Rather than attempting to implement a change in the instruction flow immediately, the processor first recognizes that flow is to be redirected from a predicted instruction flow to a correct instruction flow according to a flow control indicator. The flow control indicator may be attached to instructions flowing down the pipeline or inserted as a separate instruction in the pipeline. The pipeline is cleared of state created by instructions that do not follow the correct instruction flow, i.e., instructions that were erroneously fetched after the instruction causing the change in flow. The change in flow as indicated by the flow control indicator is implemented later in the pipeline.
Inventors
- 👤 Robert P. Colwell
- 👤 Atiq Bajwa
- 👤 Michael A. Fetterman
- 👤 Andrew F. Glew
- 👤 Glenn J. Hinton
- 👤 David B. Papworth
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 11:49
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3861; G06F9/3865; G06F9/32; G06F9/322; G06F9/323; G06F9/3836; G06F9/3842; G06F9/3844
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
67 words
In a pipelined microprocessor for executing instructions, an instruction decoder comprising: a decoding circuit generating a micro operation (uop) having a plurality of fields; an adder coupled to receive an instruction pointer of a branch instruction, the adder adding the instruction pointer to generate an absolute target address; and a multiplexing circuit multiplexing the absolute target address into one of the plurality of fields of the uop.
Claim 2
Dependent Claim
67 words
In a pipelined microprocessor for executing instructions, an instruction decoder comprising: a decoding circuit generating a micro operation (uop) having a plurality of fields; an adder coupled to receive an instruction pointer of a branch instruction, the adder adding the instruction pointer to generate an absolute target address; and a multiplexing circuit multiplexing the absolute target address into one of the plurality of fields of the uop.
Claim 3
Dependent Claim
35 words
The instruction decoder of claim 1, wherein the field is an immediate field and the instruction decoder is coupled to provide the uop, including the absolute target in the immediate field, to an execution unit.
Claim 4
Dependent Claim
87 words
In a pipelined microprocessor executing instructions and providing a macroinstruction having an address and at least one uop, an instruction decoder decoding a branch instruction having an instruction pointer and a relative target address and producing uop code and control signals, the decoder comprising: an instruction pointer register storing the instruction pointer of the branch instruction; an adder adding the macroinstruction address to the instruction pointer and generating an absolute target address, the absolute target address being multiplexed into an existing field of a decoded branch instruction.
Claim 5
Dependent Claim
87 words
In a pipelined microprocessor executing instructions and providing a macroinstruction having an address and at least one uop, an instruction decoder decoding a branch instruction having an instruction pointer and a relative target address and producing uop code and control signals, the decoder comprising: an instruction pointer register storing the instruction pointer of the branch instruction; an adder adding the macroinstruction address to the instruction pointer and generating an absolute target address, the absolute target address being multiplexed into an existing field of a decoded branch instruction.
Claim 6
Dependent Claim
14 words
The decoder according to claim 3, wherein the existing field is an immediate field.
Claim 7
Dependent Claim
78 words
In a pipelined microprocessor executing instructions, the microprocessor having a decoder circuit having an adder, a method of decoding a branch instruction, the branch instruction having an instruction pointer address and a relative target address, the method comprising the steps of: receiving the branch instruction into the decoder; adding the relative target address to a current instruction pointer; generating an absolute target address; and providing the absolute target address field as a field in the decoded branch instruction.
Claim 8
Dependent Claim
78 words
In a pipelined microprocessor executing instructions, the microprocessor having a decoder circuit having an adder, a method of decoding a branch instruction, the branch instruction having an instruction pointer address and a relative target address, the method comprising the steps of: receiving the branch instruction into the decoder; adding the relative target address to a current instruction pointer; generating an absolute target address; and providing the absolute target address field as a field in the decoded branch instruction.
Claim 9
Dependent Claim
35 words
The method according to claim 5 further comprising the step of: providing the decoded branch instruction to a reservation station with the absolute target address in the target address field of the decoded branch instruction.
Claim 10
Dependent Claim
18 words
The method according to claim 5 or 6 wherein the absolute target address generated is an immediate field.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-09-14 | 2002-03-16 | 2002-09-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-09-14 | 2006-03-16 | 2006-09-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-09-14 | 2010-03-16 | 2010-09-15 | $7700.00 | Window Closed / Lapsed |