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EP0352935A3 Expired / Lapsed EP ⏱️ 0.0 years remaining

Pipelined processor

Assignee: Fujitsu Services Ltd
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Filing: 1989-07-12
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Granted: —
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Expires: 2009-07-12
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Abstract

Abstract Data processing apparatus comprises a series of pipeline units each of which consists of a number of pipeline stages. The units are interconnected by a number of parameter files, which provide a number of slots. Whenever an instruction is initiated in the pipeline, it is allocated a slot, and retains that slot until its execution is successfully completed. Two independent streams of instructions are scheduled through the pipeline, each being allocated a fixed number of the slots. In normal operation, one of the streams has priority over the other stream. An instruction is allowed to change the process state only when it successfully terminates at the end of the pipeline, thus ensuring consistency. An instruction can be started in a lower pipeline unit as soon as it is known that its required operand will be available in time from the data slave, thus allowing the operations of these two units to be overlapped.

Inventors

  • 👤 Colin Martin Duxbury
  • 👤 Philip Vivian Rose
  • 👤 John Richard Eaton

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-01 05:55
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3861; G06F9/3865; G06F9/30145; G06F9/3016; G06F9/30167; G06F9/3836; G06F9/3851; G06F9/3863; G06F9/3867; G06F9/3875; G06F9/3885; G06F9/3889

Claims Analysis

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References Cited (Backward Citations)

US3728692A Cited
US4112489A Cited
WO1988003681A1 Cited

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