US3728692A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Instruction selection in a two-program counter instruction unit
Assignee: International Business Machines Corp
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Filing: 1971-08-31
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Granted: 1973-04-17
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Expires: 1991-08-31
Abstract
Abstract In an instruction handling unit specifically designed for pipeline processing of instructions an apparatus is disclosed which allows the instruction handling unit to process simultaneously computer instructions from two different programs. The apparatus employed for sharing the instruction unit processing capabilities among two programs performs certain checks upon the specific instructions of the two different instruction streams and determines from various machine conditions and variable program conditions which instruction will be executed within the instruction handling unit. The selection algorithm involved is designed to make maximum utilization of the instruction handling unit while preventing any one instruction stream from monopolizing the instruction handling capabilities of the instruction unit.
Inventors
- 👤 J Fennel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 21:14
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3818; G06F9/3822; G06F9/3836; G06F9/3851
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
132 words
In a pipelined processor an apparatus for controlling the processing sequence of two independent instruction streams comprising: gating means including; a logic circuit for transferring instructions from each of said instruction streams to a register connected to said gating means, depending on the instruction stream from which the preceding instruction was selected, the instruction currently residing in said register, and a control signal, interlock checking means connected to said register for determining the capability of said pipelined processor to perform instruction in said register, memory means connected to said gating means and interlock checking means for determining the instruction stream from which the instruction in said register was obtained, control signal generator means responsive to said interlocking means and said memory means for generating the control signal input for said gating means.
Claim 2
Dependent Claim
132 words
In a pipelined processor an apparatus for controlling the processing sequence of two independent instruction streams comprising: gating means including; a logic circuit for transferring instructions from each of said instruction streams to a register connected to said gating means, depending on the instruction stream from which the preceding instruction was selected, the instruction currently residing in said register, and a control signal, interlock checking means connected to said register for determining the capability of said pipelined processor to perform instruction in said register, memory means connected to said gating means and interlock checking means for determining the instruction stream from which the instruction in said register was obtained, control signal generator means responsive to said interlocking means and said memory means for generating the control signal input for said gating means.
Claim 3
Dependent Claim
41 words
The apparatus of claim 1 wherein said register is connected to said processor allowing the instruction to be processed simultaneously with the interlock check and to disregard the processing of the interlock check determines that this instruction will not be performed.
Claim 4
Dependent Claim
14 words
Performing interlock checks upon the selected instruction to determine whether it may be performed
Claim 5
Dependent Claim
14 words
Performing interlock checks upon the selected instruction to determine whether it may be performed
Claim 6
Dependent Claim
8 words
Performing the selected instruction while making interlock checks
Claim 7
Dependent Claim
8 words
Performing the selected instruction while making interlock checks
Claim 8
Independent Claim
174 words
An apparatus for sharing a pipelined processor among instructions from two independent instruction streams comprising: an independent source of instruction means for each of two independent instruction streams; a gating means connected to each of said independent source of instruction means said gating means having an output and a control signal input to the gate, said gating means operational to gate the data from only one independent source of instruction means to said output of said gating means in response to said control signal input; a register means connected to said gating means for receiving and storing an instruction gated by said gating means; an interlock check means connected to said register means for determining if the instruction in said register means can be processed by the pipelined processor; a memory means connected to said interlock check means for determining from which instruction stream present instruction was obtained; a control signal generator means responsive to said interlock check means and said memory means for generating the next control signal input for said gating means.
Claim 9
Independent Claim
174 words
An apparatus for sharing a pipelined processor among instructions from two independent instruction streams comprising: an independent source of instruction means for each of two independent instruction streams; a gating means connected to each of said independent source of instruction means said gating means having an output and a control signal input to the gate, said gating means operational to gate the data from only one independent source of instruction means to said output of said gating means in response to said control signal input; a register means connected to said gating means for receiving and storing an instruction gated by said gating means; an interlock check means connected to said register means for determining if the instruction in said register means can be processed by the pipelined processor; a memory means connected to said interlock check means for determining from which instruction stream present instruction was obtained; a control signal generator means responsive to said interlock check means and said memory means for generating the next control signal input for said gating means.
Claim 10
Dependent Claim
23 words
The apparatus of claim 3 wherein said processor contains means to allow the instruction to be processed simultaneously with the interlock check generator.
Claim 11
Dependent Claim
13 words
Defeating the performance of the selected instruction if an interlock check is detected
Claim 12
Dependent Claim
13 words
Defeating the performance of the selected instruction if an interlock check is detected
Claim 13
Dependent Claim
21 words
Preventing further selection of instructions from the instruction stream having an interlock check untIl the interlock check is no longer present
Claim 14
Dependent Claim
21 words
Preventing further selection of instructions from the instruction stream having an interlock check untIl the interlock check is no longer present
Claim 15
Independent Claim
17 words
A method of sharing a pipelined data processor between two independent instruction streams comprising the steps of:
Claim 16
Independent Claim
17 words
A method of sharing a pipelined data processor between two independent instruction streams comprising the steps of:
Claim 17
Dependent Claim
13 words
Alternating selection of instructions from instruction streams when no interlock checks are detected.
Claim 18
Dependent Claim
13 words
Alternating selection of instructions from instruction streams when no interlock checks are detected.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-04-16 | 1976-10-16 | 1977-04-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-04-16 | 1980-10-16 | 1981-04-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-04-16 | 1984-10-16 | 1985-04-17 | $7700.00 | Window Closed / Lapsed |