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Monitoring processor execution cycles to prevent task overrun in multi-task, hard, real-time system

Assignee: International Business Machines Corp
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Filing: 1994-07-13
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Granted: 2000-07-04
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Expires: 2014-07-13
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Abstract

Abstract Hard, real-time, multi-tasking system is monitored by combined hardware and software and logic to detect overrun of any task beyond a declared maximum processor cycle limit for the task. Processor execution cycles utilized by DMA or interrupt processing and not related to the task being executed are not counted. Counter hardware and control logic reduces software overhead for monitoring execution cycle utilization by a task and provides capability not only of overrun detection, but programmed cycle usage alarm, consumed cycle count and overall processor loading or utilization measurements to be made.

Inventors

  • 👤 Donald Edward Carmon

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-02 11:45
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0751; G06F11/0754; G06F11/0757; G06F11/0706; G06F11/0715; G06F11/30; G06F11/34; G06F11/3409; G06F11/3466; G06F11/348; G06F2201/00; G06F2201/805; G06F2201/865; G06F2201/88

Claims Analysis

Total Claims: 12
Claim 1
Independent Claim 83 words
In a multi-tasking program execution system, a method of monitoring task overrun conditions, the method comprising the steps of: counting only processor execution cycles associated with a specific task occurring while said specific task is executed, said specific task being executed together with one or more other tasks by a single processor; and generating a cycle counter interrupt which is one type of processor execution interrupt whenever said counting reaches a predetermined value; and stopping said counting whenever any processor execution interrupt occurs.
Claim 2
Dependent Claim 83 words
In a multi-tasking program execution system, a method of monitoring task overrun conditions, the method comprising the steps of: counting only processor execution cycles associated with a specific task occurring while said specific task is executed, said specific task being executed together with one or more other tasks by a single processor; and generating a cycle counter interrupt which is one type of processor execution interrupt whenever said counting reaches a predetermined value; and stopping said counting whenever any processor execution interrupt occurs.
Claim 3
Dependent Claim 47 words
A method as described in claim 1, further comprising: resuming said counting whenever a processor resumption of execution of said specific task occurs because said counting was stopped for a processor execution interrupt other than a cycle counter interrupt which is one type of processor execution interrupt.
Claim 4
Dependent Claim 119 words
A method as described in claim 1 or claim 2, further comprising the steps of: examining said processor execution interrupt to determine whether it is for one of said one or more other tasks which has a priority which is higher than the priority of said specific task; and storing the count reached in said counting if said processor execution interrupt is for one of said one or more other tasks which has a priority which is higher than the priority of said specific task; and resuming said counting if said processor execution interrupt is not for one of said one or more other tasks which has a priority which is higher than the priority of said specific task.
Claim 5
Dependent Claim 91 words
A method as described in claim 1 or claim 2, further comprising the steps of: establishing for each specific task a processor execution cycle count limit; comparing said processor execution cycle count limit to a count obtained and stored in a counter while counting said processor execution cycles associated with said specific task occurring while said task is executed; and if said processor execution cycle count limit has not been reached, continuing said counting but terminating execution of said specific task if said processor execution cycle count limit has been reached.
Claim 6
Dependent Claim 159 words
In a multi-tasking program execution system, a method of monitoring and controlling task execution cycle overrun, comprising the steps of: establishing a processor cycle count limit for each specific task to be executed; enabling a counter and writing said cycle count limit into said counter; counting processor execution cycles associated with a specific task while said specific task is being executed in a single processor, said specific task being executed together with one or more other tasks by said single processor; disabling said counter, stopping said counting, and generating a cycle counter interrupt which is one type of processor execution interrupt whenever said processor cycle count limit is read from said counter indicating said processor cycle count limit has been reached; stopping said counting but not disabling said counter whenever said execution system receives a processor execution interrupt which is not a cycle counter interrupt; and starting said counting whenever said execution system begins execution of said specific task.
Claim 7
Dependent Claim 159 words
In a multi-tasking program execution system, a method of monitoring and controlling task execution cycle overrun, comprising the steps of: establishing a processor cycle count limit for each specific task to be executed; enabling a counter and writing said cycle count limit into said counter; counting processor execution cycles associated with a specific task while said specific task is being executed in a single processor, said specific task being executed together with one or more other tasks by said single processor; disabling said counter, stopping said counting, and generating a cycle counter interrupt which is one type of processor execution interrupt whenever said processor cycle count limit is read from said counter indicating said processor cycle count limit has been reached; stopping said counting but not disabling said counter whenever said execution system receives a processor execution interrupt which is not a cycle counter interrupt; and starting said counting whenever said execution system begins execution of said specific task.
Claim 8
Dependent Claim 133 words
Apparatus for detecting task execution cycle overrun in a multi-tasking processor system, comprising: counting means for counting processor execution cycles associated with a specific task, said specific task being executed together with one or more other tasks by a single processor; logic means connected to said counting means to control said counting means said logic means comprising: means for enabling said counting means; means for disabling said counting means when a cycle counter interrupt which is one type of processor execution interrupt occurs; means for starting said counting means whenever said multi-tasking processor system begins execution of said specific task and said counting means is not disabled; and means for stopping said counting means but not disabling said counting means whenever a processor execution interrupt which is not a cycle counter interrupt occurs.
Claim 9
Dependent Claim 133 words
Apparatus for detecting task execution cycle overrun in a multi-tasking processor system, comprising: counting means for counting processor execution cycles associated with a specific task, said specific task being executed together with one or more other tasks by a single processor; logic means connected to said counting means to control said counting means said logic means comprising: means for enabling said counting means; means for disabling said counting means when a cycle counter interrupt which is one type of processor execution interrupt occurs; means for starting said counting means whenever said multi-tasking processor system begins execution of said specific task and said counting means is not disabled; and means for stopping said counting means but not disabling said counting means whenever a processor execution interrupt which is not a cycle counter interrupt occurs.
Claim 10
Dependent Claim 23 words
Apparatus as described in claim 6, further comprising: means for generating said cycle counter interrupt whenever said counting means reaches a predetermined value.
Claim 11
Dependent Claim 87 words
Apparatus for monitoring execution task overrun conditions in a multi-tasking program execution system, the apparatus comprising: means for counting only processor execution cycles associated with a specific task occurring while said specific task is executed, said specific task being executed together with one or more other tasks by a single processor; means for generating a cycle counter interrupt which is one type of processor execution interrupt whenever said counting means reaches a predetermined value; and means for stopping said counting means whenever any processor execution interrupt occurs.
Claim 12
Dependent Claim 87 words
Apparatus for monitoring execution task overrun conditions in a multi-tasking program execution system, the apparatus comprising: means for counting only processor execution cycles associated with a specific task occurring while said specific task is executed, said specific task being executed together with one or more other tasks by a single processor; means for generating a cycle counter interrupt which is one type of processor execution interrupt whenever said counting means reaches a predetermined value; and means for stopping said counting means whenever any processor execution interrupt occurs.

References Cited (Backward Citations)

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2003-07-04 2004-01-03 2004-07-04 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2007-07-04 2008-01-03 2008-07-04 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2011-07-04 2012-01-03 2012-07-04 $7700.00 Window Closed / Lapsed

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