EP0863462A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Processor capable of efficiently executing many asynchronous event tasks
Assignee: Panasonic Corp
•
Filing: 1998-03-03
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Granted: —
•
Expires: 2018-03-03
Abstract
Abstract The counter 52 is set with an initial value of "1" and is a counter with a maximum value of "4". This counter 52 increments the count value held by the flip-flop 51 in synchronization with a clock signal so that the count value changes as shown by the progression 1,2,3,4,1, 2,3,4. This clock signal is also used by the instruction decode control unit 11 to control the execution of instructions, with the counting by the counter 52 being performed once for each instruction execution performed by the instruction decode control unit 11. The comparator 54 compares the count value counted by the counter 52 with the maximum value "4", and when the values match, sets the task switching signal chg_task_ex at a "High" value, so that the processing switches to the execution of the next task.
Inventors
- 👤 Takaharu Tanaka
- 👤 Kyoshi Maenobu
- 👤 Kosuke Yoshioka
- 👤 Makoto Hirai
- 👤 Tokuzo Kiyohara
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 17:36
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4843; G06F9/4881; G06F9/30; G06F9/30003; G06F9/30076; G06F9/30087; G06F9/3009; G06F9/38; G06F9/3836; G06F9/3851; H; H04; H04N; H04N19/00; H04N19/42; H04N19/60; H04N19/61
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
97 words
A processor for processing n tasks, the processor
comprising: execution task indicating means for outputting a
task identifier for one of the n tasks and, when execution
of instructions has been performed for a number of
instructions assigned to a task corresponding to the
outputted task identifier, outputting a next task
identifier in a predetermined order; instruction indicating means for indicating one
instruction at a time in order in the task corresponding
to the outputted task identifier outputted by the
execution task indicating means; and executing means for executing the instruction
indicated by the instruction indicating means.
Claim 2
Dependent Claim
83 words
The processor of Claim 1, wherein the execution task indicating means includes: a task switching signal generator for counting a
count number which is a number of times instructions are
issued and for issuing a task switching signal when the
count number becomes equal to the number of instructions
assigned to the task corresponding to the outputted task
identifier; and a task identifier outputting unit for generating the
next task identifier in the predetermined order when the
task switching signal has been issued.
Claim 3
Dependent Claim
183 words
The processor of Claim 2, wherein the instruction indicating means includes: n address registers that each correspond to one of
the n tasks and that store a start address that should be
read next for a corresponding task; a register selecting unit for selecting, when the
next task identifier has been outputted by the execution
task indicating means, an address register out of the n
address registers that corresponds to the outputted next
task identifier; a read address generating unit for setting a start
address stored in the address register selected by the
register selecting unit as a starting read address and
successively updating the read address until there is a
change in the task identifier; and an address register updating unit for rewriting the
start address in the address register that was previously
selected by the register selecting unit using a read
address updated by the read address generating unit when
task switching is performed, wherein the executing means executes an instruction
whose address is the read address that has been written
into the address register by the read address generating
unit.
Claim 4
Dependent Claim
64 words
The processor of Claim 2, wherein the task switching signal generator
includes: a counter for counting a clock pulse; and a comparator for comparing a count value of the
counter with the number of instructions that has been
assigned to a presently selected task, and for outputting
a task switching signal and resetting the counter when the
count value matches the number of instructions.
Claim 5
Dependent Claim
95 words
The processor of Claim 4, wherein the task switching signal generator
includes: a number of instructions storing unit for storing at
least two different numbers of instructions; and a number of instructions selecting unit for
selecting one of the numbers of instructions stored in the
number of instructions storing unit according to the task
identifier indicated by the execution task indicating
means, wherein the number of instructions selected by the
number of instructions selecting unit is inputted into the
comparator to be used as the number of instructions that
is compared with the count value.
Claim 6
Dependent Claim
169 words
The processor of Claim 5, wherein the numbers of instructions stored by the
number of instructions storing unit include a first fixed
number of instructions and a second fixed number of
instructions, the second fixed number of instructions
being lower than the first fixed number of instructions, wherein the instruction indicating means includes a
penalty task storing unit for storing an identifier of at
least one penalty task, a penalty task being a task out of
the n tasks that should be assigned the second fixed
number of instructions, and wherein the number of instructions selecting unit
includes: a judging unit for judging, when the execution task
indicating means outputs the next task identifier, whether
the outputted next task identifier corresponds to an
identifier for a penalty task; and a fixed number outputting unit for outputting the
second fixed number of instructions stored by the number
of instructions storing unit when the judging unit judges
that the outputted next task identifier corresponds to an
identifier for a penalty task.
Claim 7
Dependent Claim
133 words
The processor of Claim 6, wherein at least one task in the n tasks includes a
state monitoring instruction that indicates a presence of
a phenomenon as a condition, wherein the executing means includes: decoding means for decoding an instruction at the
read address generated by the read address generating
unit; and calculating means for executing, when the
instruction decoded by the decoding means is a state
monitoring instruction, a calculation to confirm whether a
phenomenon, whose presence is indicated as a condition by
the state monitoring instruction, is present, and wherein when a calculation result of the calculating
means is that the indicated phenomenon is not present, the
penalty task storing unit stores a task identifier of a
task that includes the state monitoring instruction as an
identifier of a penalty task.
Claim 8
Dependent Claim
105 words
An information processing system including the
processor of Claim 7, a buffer, and a memory, wherein the processor includes a plurality of state
monitoring registers showing a state of the memory and the
buffer, wherein each state monitoring instruction includes
an indication of one out of the plurality of state
monitoring registers and an indication of an immediate
value, and wherein when the decoding result of the decoding
means is a state monitoring instruction, the calculating
means performs the calculation using a stored value of the
state monitoring register indicated by the state
monitoring instruction and the immediate value indicated
by the state monitoring instruction.
Claim 9
Dependent Claim
76 words
The processor of Claim 2, wherein the task identifier outputting unit
includes: an order storing unit for storing an output order
for outputting each task identifier as the predetermined
order of the n tasks; and a selection outputting unit for outputting, when a
task switching signal has been issued by the task
switching signal generator, a task identifier which is
next in the output order stored by the order storing unit
to the instruction indicating means.
Claim 10
Dependent Claim
191 words
The processor of Claim 9, wherein at least one of the n tasks includes an
emergency announcement instruction that indicates that a
present task requires emergency treatment, wherein the executing means includes decoding means
for decoding the instruction indicated by the instruction
indicating means, and wherein the execution task indicating means
includes: an emergency task register for storing, when a
decoding result of the decoding means is an emergency
announcement instruction, a task identifier of a task that
is indicated by the decoded emergency announcement
instruction as a task that requires emergency treatment;
and an output ratio control unit which (1) when no task identifier for an emergency task is
stored in the emergency task register, forwards the task
identifier outputted by the selection outputting unit to
the executing means when a task switching signal is
issued, and (2) when a task identifier for an emergency task is
stored in the emergency task register, forwards, at a
ratio of once every m task switching signals (where m≥2),
the task identifier for the emergency task stored in the
emergency task register to the executing means when a task
switching signal is issued.
Claim 11
Dependent Claim
197 words
The processor of Claim 9, wherein at least one of the n tasks includes an
emergency announcement instruction that indicates that a
present task requires emergency treatment, and wherein the execution task indicating means
includes: monitoring means for monitoring whether a
predetermined signal has been inputted from a periphery of
the processor to judge whether the periphery of the
processor is in an emergency state; an emergency task register for storing an identifier
of an emergency task that should be given emergency
treatment while the predetermined signal shows that the
periphery of the processor is in an emergency state; and an output ratio control unit which (1) when no task identifier for an emergency task is
stored in the emergency task register, forwards the task
identifier outputted by the selection outputting unit to
the executing means when a task switching signal is
issued, and (2) when a task identifier for an emergency task is
stored in the emergency task register, forwards, at a
ratio of once every m task switching signals (where m≥2),
the task identifier for the emergency task stored in the
emergency task register to the executing means when a task
switching signal is issued.
Claim 12
Dependent Claim
81 words
The processor of Claim 11, wherein the order storing unit includes an n-bit
register for storing an n-bit array, each bit in the n-bit
array corresponding to one of task identifiers of the n
tasks, and wherein the output order of the task identifiers is
decided by ordinal positions of the bits in the n-bit
array that correspond to the task identifiers, calculated
from one of a most significant bit end and a least
significant bit end of the n-bit array.
Claim 13
Dependent Claim
198 words
The processor of Claim 12, wherein a bit in the n-bit array which corresponds
to a task identifier that has been outputted is set at "1"
and a bit in the n-bit array which corresponds to a task
identifier that is yet to be outputted is set at "0", wherein the task identifier outputting unit
includes: a bit setting unit for setting, when the next task
identifier in the predetermined order has been outputted
by the selection outputting unit, a bit in the n-bit array
that corresponds to the outputted next task identifier to
"1"; and a bit resetting unit for resetting the all bits in
the n-bit array to "0" when all bits in the n-bit array
have been set at "1" by the bit setting unit, and wherein the selection outputting unit includes a
priority encoder which, based on a closest bit position to
one of a most significant bit end or a least significant
bit end of the n-array stored in the n-bit register to
have a bit value of "0" and not "1", generates the next
task identifier to be outputted and outputs the generated
next task identifier to the execution task indicating
means.
Claim 14
Dependent Claim
55 words
The processor of Claim 13, wherein the task identifier outputting unit includes
a mask unit for setting, when the emergency task register
stores a task identifier of a task including an emergency
announcement instruction, a bit in the n-bit array that is
assigned to the task identifier stored in the emergency
task register to "1".
Claim 15
Dependent Claim
91 words
The processor of Claim 14, wherein the processor is provided in an AV decoder
system that decodes video streams, wherein at least one emergency task is a task that
outputs a result of decoding one of the video streams when
the decoding of the one of the video streams has been
completed by the AV decoder system, and wherein the predetermined signal monitored by the
monitoring means is at least one of a horizontal return
interval signal and vertical return interval signal for a
display used to display an image signal.
Claim 16
Dependent Claim
64 words
The processor of Claim 11, wherein the task switching signal generator
includes: a counter for counting a clock pulse; and a comparator for comparing a count value of the
counter with the number of instructions that has been
assigned to a presently selected task, and for outputting
a task switching signal and resetting the counter when the
count value matches the number of instructions.
Claim 17
Dependent Claim
95 words
The processor of Claim 16, wherein the task switching signal generator includes: a number of instructions storing unit for storing at
least two different numbers of instructions; and a number of instructions selecting unit for
selecting one of the numbers of instructions stored in the
number of instructions storing unit according to the task
identifier indicated by the execution task indicating
means, wherein the number of instructions selected by the
number of instructions selecting unit is inputted into the
comparator to be used as the number of instructions that
is compared with the count value.
Claim 18
Dependent Claim
187 words
The processor of Claim 17, wherein the numbers of instructions stored by the
number of instructions storing unit include a first fixed
number of instructions and a second fixed number of
instructions, the second fixed number of instructions
being higher than the first fixed number of instructions, wherein the task identifier outputting unit
includes: an emergency task storing unit for storing at least
one task identifier of an emergency task that should be
assigned the second fixed number of instructions when the
task identifier of the emergency task is next outputted,
and wherein the number of instructions selecting unit
includes: a judging unit for judging, when the monitoring
means judges that the predetermined signal inputted from
the periphery of the processor is in an emergency state
and a task identifier has been outputted by the execution
task indicating means, whether the outputted task
identifier is a task identifier for an emergency task; and a fixed number outputting unit for outputting the
second fixed number of instructions to the comparator when
the judging unit judges that the outputted task identifier
is a task identifier for an emergency task.
Claim 19
Dependent Claim
139 words
The processor of Claim 9, wherein at least one of the n tasks includes a
sleep-inducing instruction which sets an execution state
of a task into a sleep state, wherein the executing means includes decoding means
for an instruction which is indicated by the instruction
indicating means as the next instruction to be executed, wherein the execution task indicating means further
includes a sleeping task register for storing, when a
decoding result of the decoding means is a sleep-inducing
instruction, a task identifier of a task indicated by the
sleep-inducing instruction as a task that should be
treated as a sleeping task, and wherein when a next task identifier stored in the
order storing unit is a task identifier for a sleeping
task, the selection outputting means outputs a task
identifier following the task identifier for the sleeping
task.
Claim 20
Dependent Claim
63 words
The processor of Claim 19, wherein at least one task includes a forcible
removal instruction that removes a sleep state for another
task, and wherein the execution task indicating means includes
a deleting unit for deleting, when a decoding result of
the decoding means is a forcible removal instruction, a
task identifier identified by the forcible removal
instruction from the sleeping task register.
Claim 21
Dependent Claim
81 words
The processor of Claim 20, wherein the order storing unit includes an n-bit
register for storing an n-bit array, each bit in the n-bit
array corresponding to one of task identifiers of the n
tasks, and wherein the output order of the task identifiers is
decided by ordinal positions of the bits in the n-bit
array that correspond to the task identifiers, calculated
from one of a most significant bit end and a least
significant bit end of the n-bit array.
Claim 22
Dependent Claim
198 words
The processor of Claim 21, wherein a bit in the n-bit array which corresponds
to a task identifier that has been outputted is set at "1"
and a bit in the n-bit array which corresponds to a task
identifier that is yet to be outputted is set at "0", wherein the task identifier outputting unit
includes: a bit setting unit for setting, when the next task
identifier in the predetermined order has been outputted
by the selection outputting unit, a bit in the n-bit array
that corresponds to the outputted next task identifier to
"1"; and a bit resetting unit for resetting the all bits in
the n-bit array to "0" when all bits in the n-bit array
have been set at "1" by the bit setting unit, and wherein the selection outputting unit includes a
priority encoder which, based on a closest bit position to
one of a most significant bit end or a least significant
bit end of the n-array stored in the n-bit register to
have a bit value of "0" and not "1", generates the next
task identifier to be outputted and outputs the generated
next task identifier to the execution task indicating
means.
Claim 23
Dependent Claim
88 words
The processor of Claim 22, wherein the execution task indicating means
includes: a masking unit for masking, when the emergency task
register is storing a task identifier for a task that
includes a sleep-inducing instruction, a bit assigned to
the sleeping task out of the n-bit array to "1"; and an unmasking unit for setting, when a decoding
result of the decoding means is a forcible removal
instruction, a bit in the n-bit array that is assigned to
the task indicated by the forcible removal instruction to
"0".
Claim 24
Dependent Claim
208 words
A processor for executing n tasks, the processor
comprising: number of cycles storing means which stores a number
of cycles which is assigned to every task in the n tasks,
the number of cycles being a maximum number of cycles from
a start of execution of a task to a task switching to a
next task, and a total time for a maximum number of cycles
for all n tasks being set so as to be shorter than an
interval for which an asynchronous phenomenon is present; a counter for counting a count value based on a
clock; comparing means for comparing the count value of the
counter with the number of cycles stored in the number of
cycles storage means, and issuing a task switching signal
and a counter reset signal when the count value of the
counter is equal to the number of cycles; selecting means for selecting a task when a task
switching signal is inputted according to a predetermined
order for selecting tasks; instruction indicating means for successively
indicating instructions in a task selected by the
selecting means one instruction at a time; and executing means for executing an instruction
indicated by the instruction indicating means for the task
selected by the selecting means.
Claim 25
Dependent Claim
82 words
The processor of Claim 24, wherein one of the tasks is assigned processing
relating to the asynchronous phenomenon, and wherein the number of cycles, given by a product of
a number of cycles assigned to the task assigned
processing relating to the asynchronous phenomenon and a
number of times the task assigned processing relating to
the asynchronous phenomenon is selected during an
occurrence interval of the asynchronous phenomenon, is
greater than a required amount of processing in response
to the asynchronous phenomenon.
Claim 26
Dependent Claim
244 words
The processor of Claim 25, wherein the processor is provided in an AV (Audio-Visual)
decoder system that also comprises a decoder unit
for decoding audio streams and video streams, a local
buffer that is used in decoding processing by the decoder
unit, and an external memory, wherein n equals four, wherein a first task in the four tasks is a task for
extracting an audio stream and a video stream from a
bitstream inputted from a periphery of the Av decoder
system and for writing the extracted audio stream and
video stream into the external memory, wherein a second task in the four tasks is a task
for supplying an audio stream and a video stream to be
processed next from the external memory to the decoder
unit as the decoding processing by the decoder unit
progresses, wherein a third task in the four tasks is a task for
reading video data out of a decoding result of the decoder
unit from the external memory and outputting the read
video data to an externally connected display in
synchronization with a synchronization signal of the
display, wherein a fourth task in the four tasks is a task
for reading audio data out of a decoding result of the
decoder unit from the external memory and outputting the
read audio data to an externally connected speaker
apparatus with a predetermined synchronization, and wherein the number of cycles assigned to each of the
four tasks is four.
Claim 27
Dependent Claim
109 words
A processor for executing n tasks, comprising: task selecting means for successively selecting one
of the n tasks at intervals of a predetermined number of
cycles; instruction indicating means, having n sets of
instruction indicating information which each correspond
to a different one of the n tasks, which validates a set
of instruction indicating information that corresponds to
the task selected by the task selecting means and which
dynamically generates information indicating which
instruction should be read next according to the validated
set of instruction indicating information; and executing means for reading the instruction
indicated by the information generated by the instruction
indicating means and executing the read instruction.
Claim 28
Dependent Claim
158 words
The processor of Claim 27, wherein the instruction indicating means includes: n address registers which each correspond to a
different one of the n tasks, each address register
storing an address value to be read next for a
corresponding task as the set of instruction indicating
information for the corresponding task; a register selecting unit for selecting an address
register corresponding to the task selected by the task
selecting means and having an address value in the
selected address register outputted; a count value register for storing, when an address
register has been selected by the register selecting unit,
the address value stored in the selected address register
as a starting count value; an incrementor for incrementing the count value
stored in the count value register in each cycle; and a read address storing unit for storing the count
value incremented by the incrementor as an updated value
for information that indicates an instruction to be read
next.
Claim 29
Dependent Claim
124 words
The processor of Claim 28, wherein the instruction indicating means includes: a first selector for forwarding the count value
incremented by the incrementor to the read address storing
unit to have the count value stored in the read address
storing unit and, when a task has been selected by the
task selecting unit, selectively outputting an address
value in the address register corresponding to the
selected task to have the address value stored in the read
address storing unit; and a first rewriting uniL which, when switching is
performed to a next task, uses the count value stored in
the count value register to rewrite the address value
stored in the address register that was selected by the
register selecting unit before the switching.
Claim 30
Dependent Claim
143 words
The processor of Claim 29, wherein at least one task includes a switching
instruction that indicates a task switching should be
performed, wherein the executing means includes decoding means
for decoding an instruction specified by the address
stored in the read address storing unit, wherein instruction indicating means further
includes a second rewriting unit which, when a decoding
result of the decoding means is a task switching
instruction, uses a set of instruction indication
information stored in the read address storing unit to
rewrite an address value stored in the address register
selected by the register selecting unit before task
switching, wherein when the decoding result of the decoding
means is a task switching instruction, the first selector
selects a read address of an address register
corresponding to a next task and has the read address
stored in the read address storing unit.
Claim 31
Dependent Claim
75 words
The processor of Claim 30, wherein at least one task includes a branch
instruction that indicates an absolute address as a branch
destination, wherein the instruction indicating means includes: a third rewriting unit which, when the decoding
result of the decoding means is a branch instruction, uses
an absolute address in the branch instruction to rewrite
an address value stored in the address register that was
selected by the register selecting unit before task
switching.
Claim 32
Dependent Claim
95 words
The processor of Claim 31, wherein at least one task includes a branch
instruction that has an indirect address indication as a
branch destination, wherein the instruction indicating means includes: a fourth rewriting unit which, when the decoding
result of the decoding means is a branch instruction that
has an indirect address indication and a branch
destination address has been calculated by instruction
execution by the executing means, uses the calculated
branch destination address to rewrite an address value
stored in the address register that was selected by the
register selecting unit before task switching.
Claim 33
Dependent Claim
71 words
The processor of Claim 32, wherein the executing means includes: a general register set which is composed of n*m
general registers, wherein m general registers are
assigned to each of the n tasks; a calculation executing unit for executing, when a
task has been selected by the task selecting unit, a
calculation for an instruction included in the selected
task using the m general registers which correspond to the
selected task.
References Cited (Backward Citations)
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