EP0403729A2
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Digital-signal processing apparatus
Assignee: Sony Corp
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Filing: 1990-02-23
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Granted: —
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Expires: 2010-02-23
Abstract
Abstract A digital signal processing apparatus includes two or more address registers (8a, 8b; 11a, 11b; 14a, 14b) associated with at least one of an instruction memory (3), a data memory (4), or a coefficient memory (5) and two or more data registers (17a, 17b) associated with a computing block (6), and these two or more registers are duty cycled switched between different jobs being simultaneously processed by the computing block (6) to enable efficient processing on a single chip of jobs that can be processed with different processing speeds, such as jobs suited for high speed processing or low speed processing.
Inventors
- 👤 Taro C/O Sony Corporation Nakagawa
- 👤 Akira C/O Sony Corporation Sakamoto
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 19:04
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3885; G06F9/3888; G06F9/3836; G06F9/3851; G06F9/46; G06F9/461; G06F9/462
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
125 words
A digital signal processing apparatus for simultaneously processing two or more jobs and comprising at least an instruction memory (3), a data memory (4) and a computing block (6), operatively connected to each other and wherein the improvement resides in that (a) two or more registers (8a, 8b; 11a, 11b; 14a, 14b; 17a, 17b) are associated with at least one of the instruction memory (3), data memory (4) or the computing block (6), and (b) switching means (2, 9, 12, 15, 18) are provided for cyclically switching between the two or more registers to connect them to the associated one of the instruction memory (3), data memory (4) or the computing block (6) depending upon which job is being processed in part at that instant.
Claim 2
Dependent Claim
125 words
A digital signal processing apparatus for simultaneously processing two or more jobs and comprising at least an instruction memory (3), a data memory (4) and a computing block (6), operatively connected to each other and wherein the improvement resides in that (a) two or more registers (8a, 8b; 11a, 11b; 14a, 14b; 17a, 17b) are associated with at least one of the instruction memory (3), data memory (4) or the computing block (6), and (b) switching means (2, 9, 12, 15, 18) are provided for cyclically switching between the two or more registers to connect them to the associated one of the instruction memory (3), data memory (4) or the computing block (6) depending upon which job is being processed in part at that instant.
Claim 3
Dependent Claim
58 words
The digital signal processing apparatus according to claim 1, wherein the two or more registers include address registers (11a, 11b) which are associated with the data memory (4) and wherein the address registers have inputs and outputs and the switching means (2, 12) connects the outputs of the two or more address registers to the data memory (4).
Claim 4
Dependent Claim
60 words
The digital signal processing apparatus according to claim 1 or 2, wherein the two or more registers include data registers (17a, 17b) which are associated with the computing block (6) and wherein the data registers have inputs and outputs and the switching means (2, 18) connects the inputs of the two or more data registers to the computing block (6).
Claim 5
Dependent Claim
48 words
The digital signal processing apparatus according to anyone of claims 1 to 3, wherein the two or more registers include address registers (11a, 11b) which are associated with the data memory (4) and two or more data registers (17a, 17b) which are associated with the computing block (6).
Claim 6
Dependent Claim
38 words
The digital signal processing apparatus according to anyone of claims 1 to 4 further comprising a coefficient memory (5) and the two or more registers include address registers (14a, 14b) which are associated with the coefficient memory (5).
Claim 7
Dependent Claim
74 words
The digital signal processing apparatus according to anyone of claims 1 to 5, wherein the computing block (6) operates according to instruction cycle clocks and the switching means comprises a plurality of separate switches for sequentially and simultaneously switching the output of the registers in correspondence with one or more of the instruction cycle clocks to thereby allocate the registers to the processing of each job during one or more instruction cycle clock periods.
References Cited (Backward Citations)
No citation records indexed.
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