Power down system and method for pipelined logic functions

Claim 3

The method as recited in claim 1, further comprising the steps of: transferring said request signal from said first stage to a second stage in said pipeline; and processing data received from said first stage in said second stage in response to receipt of said request signal in said second stage.

Claim 4

The method as recited in claim 2, wherein said first and second stages are coupled to a data bus, wherein said step of receiving and processing data in said first stage when said request signal indicates that said received data is valid further comprises the steps of: receiving first data from said data bus when said request signal indicates that said first data is valid; storing said first data in said first stage; and performing a logical function on said first data to produce second data.

Claim 5

The method as recited in claim 3, wherein said step of processing data received from said first stage in said second stage in response to receipt of said request signal in said second stage further comprises the steps of: transmitting said second data onto said data bus; receiving said second data from said data bus in response to receipt of said request signal in said second stage; storing said second data in said second stage; and performing a logical function on said second data to produce third data.

Claim 6

The method as recited in claim 2, wherein said step of processing data received from said first stage in said second stage in response to receipt of said request signal in said second stage further comprises the steps of: receiving a second clock signal; and applying said second clock signal to said second stage in response to receipt of said request signal from said first stage into said second stage.

Claim 7

The method as recited in claim 1, wherein said steps of receiving and processing data in said first stage are not performed when said request signal indicates that said received data is invalid.

Claim 8

The method as recited in claim 1, further comprising the steps of: removing said clock signal from said first stage when said request signal indicates that said received data is invalid; and transferring said request signal indicating that said received data is invalid to a subsequent stage coupled to said first stage.

Claim 9

The method as recited in claim 7, further comprising the step of: clocking said request signal indicating that said received data is invalid down said pipeline sequentially through subsequent stages of said pipeline, wherein said clocking step results in removal of clock pulses from said subsequent stages in a sequential manner.

Claim 12

The system as recited in claim 9, further comprising: means for transferring said request signal from said first stage to a second stage in said pipeline; and means for processing data received from said first stage in said second stage in response to receipt of said request signal in said second stage.

Claim 13

The system as recited in claim 10, wherein said first and second stages are coupled to a data bus, wherein said comprises: first register receives said first data from said data bus when said request signal indicates that said first data is valid, said first register storing said first data; and wherein said second logic circuit performs a logical function on said first data to produce second data.

Claim 14

The system as recited in claim 11, wherein said means for processing data received from said first stage in said second stage in response to receipt of said request signal in said second stage further comprises: means for transmitting said second data onto said data bus; a second register for receiving said second data from said data bus in response to receipt of said request signal in said second stage, said second register storing said second data in said second stage; and a third logic circuit for performing a logical function on said second data to produce third data.

Claim 15

The system as recited in claim 12, wherein said means for processing data received from said first stage in said second stage in response to receipt of said request signal in said second stage further comprises: receiving a second clock pulse; and applying said second clock pulse to said second stage in response to receipt of said request signal from said first stage into said second stage.

Claim 16

The system as recited in claim 13, wherein said applying means is an AND circuit.

Claim 17

The system as recited in claim 10, wherein said transferring means further comprises: a flip-flop having a first input for receiving said request signal from a previous stage in said pipeline, a second input for receiving a clock signal, and an output means for transmitting said request signal to said second stage in response to said clock signal.

Claim 18

A data processing system including a processor coupled via a bus to a memory device, a storage device, an input device and an output device, wherein said processor includes pipelined logic circuitry of two or more stages coupled to a data bus, said system comprising: means for receiving a first clock signal and a request signal; first logic circuitry coupled to said data bus; means, coupled to said means for receiving said first clock signal and said request signal, for applying said first clock signal to said first logic circuitry when said request signal indicates that first data residing on said data bus is valid data; means, responsive to receipt by said first logic circuitry of said first clock signal, for inputting said first data into said first logic circuitry for processing by said first logic circuitry in order to produce second data; means for outputting said second data from said first logic circuitry to said data bus; means for receiving a second clock signal; means for transferring said request signal to said means for receiving said second clock signal; second logic circuitry coupled to said data bus; means, coupled to said means for receiving said second clock signal, for applying said second clock signal to said second logic circuitry; means, responsive to receipt by said second logic circuitry of said second clock signal, for inputting said second data into said second logic circuitry for processing by said second logic circuitry in order to produce third data; means for outputting said third data from said second logic circuitry to said data bus.

Claim 19

A data processing system including a processor coupled via a bus to a memory device, a storage device, an input device and an output device, wherein said processor includes pipelined logic circuitry of two or more stages coupled to a data bus, said system comprising: means for receiving a first clock signal and a request signal; first logic circuitry coupled to said data bus; means, coupled to said means for receiving said first clock signal and said request signal, for applying said first clock signal to said first logic circuitry when said request signal indicates that first data residing on said data bus is valid data; means, responsive to receipt by said first logic circuitry of said first clock signal, for inputting said first data into said first logic circuitry for processing by said first logic circuitry in order to produce second data; means for outputting said second data from said first logic circuitry to said data bus; means for receiving a second clock signal; means for transferring said request signal to said means for receiving said second clock signal; second logic circuitry coupled to said data bus; means, coupled to said means for receiving said second clock signal, for applying said second clock signal to said second logic circuitry; means, responsive to receipt by said second logic circuitry of said second clock signal, for inputting said second data into said second logic circuitry for processing by said second logic circuitry in order to produce third data; means for outputting said third data from said second logic circuitry to said data bus.

Claim 20

The system as recited in claim 16, wherein said means for receiving said first clock signal and said means for receiving said second clock signal are coupled to a clock bus.