US4685058A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Two-stage pipelined execution unit and control stores
Assignee: Fujitsu IT Holdings Inc
•
Filing: 1986-08-15
•
Granted: 1987-08-04
•
Expires: 2006-08-15
Abstract
Abstract A two control store scheme with instruction execution overlay is shown in a data processing system execution unit having a two-state pipeline. The first control store controls the first-stage facilities during the first cycle of instruction execution and points to the initial location of the second control store. The second control store controls the second-state facilities during the final cycle of instruction execution. The second control store also controls the facilities of both stages during the intermeidate cycles of instruction requiring more than two cycles to execute. Because the second control store controls only the second-stage facilities during the final cycle, execution of the first cycle of the following instruction can take place concurrently within the first-stage facilities under the control of the first control store.
Inventors
- 👤 Hsiao-Peng S. Lee
- 👤 Stephen J. Rawlinson
- 👤 Stephen S. Si
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 15:34
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3885; G06F9/3889; G06F9/22; G06F9/26; G06F9/262; G06F9/268; G06F9/28; G06F9/3867
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
388 words
A data processing system having an instruction unit generating a sequence of execution unit commands and a means for supplying operands, comprising: a first control store including a plurality of first storage locations addressed in response to execution unit commands for storing first microprogram control words in the storage locations and supplying the first microprogram control words from addressed locations, the first microprogram control words including a first facility control code field and a second stage command field; a second control store including a plurality of second storage locations addressed in response to second stage addresses, for storing second microprogram control words in the second storage locations and supplying the second microprogram control words from addressed locations, the second microprogrammed control words including a first facility control code field, a second facility control code field and a branch field; address selecting means, connected to receive the second stage command field and the branch field from addressed locations in the first control store and the second control store, for selecting the second stage command field or the branch field for supply as a second stage address in response to an address selector control signal; code selecting means, connected to receive the first facility control code field from addressed locations in the first control store and the first facility control code field from addressed locations in the second control store, for selecting a first facility control code field from the first or second control stores for supply as a first facility control code in response to a code selector control signal; first decoding means, connected to the code selector means, for decoding the first facility control code to generate first control signals and the address and code selector control signals; second decoding means, connected to the second control store, for decoding the second facility control code field to generate second control signals; and execution means, connected to receive the operands, for executing the first and second control signals, the execution means including a first facility responsive to the first control signals and a second facility responsive to the second control signals connected in pipeline fashion whereby the first facility is adapted to execute first control signals for a given execution unit command in the same cycle that the second facility executes second control signals for a preceding execution unit command.
Claim 2
Dependent Claim
388 words
A data processing system having an instruction unit generating a sequence of execution unit commands and a means for supplying operands, comprising: a first control store including a plurality of first storage locations addressed in response to execution unit commands for storing first microprogram control words in the storage locations and supplying the first microprogram control words from addressed locations, the first microprogram control words including a first facility control code field and a second stage command field; a second control store including a plurality of second storage locations addressed in response to second stage addresses, for storing second microprogram control words in the second storage locations and supplying the second microprogram control words from addressed locations, the second microprogrammed control words including a first facility control code field, a second facility control code field and a branch field; address selecting means, connected to receive the second stage command field and the branch field from addressed locations in the first control store and the second control store, for selecting the second stage command field or the branch field for supply as a second stage address in response to an address selector control signal; code selecting means, connected to receive the first facility control code field from addressed locations in the first control store and the first facility control code field from addressed locations in the second control store, for selecting a first facility control code field from the first or second control stores for supply as a first facility control code in response to a code selector control signal; first decoding means, connected to the code selector means, for decoding the first facility control code to generate first control signals and the address and code selector control signals; second decoding means, connected to the second control store, for decoding the second facility control code field to generate second control signals; and execution means, connected to receive the operands, for executing the first and second control signals, the execution means including a first facility responsive to the first control signals and a second facility responsive to the second control signals connected in pipeline fashion whereby the first facility is adapted to execute first control signals for a given execution unit command in the same cycle that the second facility executes second control signals for a preceding execution unit command.
Claim 3
Dependent Claim
86 words
The data processing system of claim 1, wherein the means for supplying operands includes an operand word register; and the first facility is connected to receive operands from the operand word register, the second facility is connected to the first facility for receiving operands as processed by the first facility, and the second facility supplies resulting data in a result register; and further including clock control means connected to the first facility, second facility and result register for controlling the timing of execution in pipeline fashion.
Claim 4
Dependent Claim
169 words
The data processing system of claim 1 wherein the instruction unit generates a command-valid signal in association with each valid command in the sequence of execution unit commands, and wherein; the address selecting means and the code selecting means are further responsive to the command-valid signal such that the address selecting means selects the second stage command field when the address selector control signal and the command-valid signal are asserted; and selects the branch field when the address selector control signal is asserted and the command-valid signal is not asserted, or when the address selector control signal is not asserted; and the code selecting means selects the first facility control code field from the first control store when the code selector control signal is asserted and the command-valid signal is asserted; and selects the first facility control code field from the second control store when the code selector control signal is asserted and the command-valid signal is not asserted, or when the code selector control signal is not asserted.
Claim 5
Dependent Claim
73 words
The data processing system of claim 1 wherein the first control signals include a test data valid signal and the means for supplying operands generates a data valid signal when valid data is available, and further including clock control means, responsive to the test data valid signal and data valid signal for delaying execution by the execution means in response to a test data valid signal until a data valid signal is received.
Claim 6
Dependent Claim
57 words
The data processing system of claim 3 wherein the first control signals further include a result register clock signal and the second facility includes a result register for supplying resulting operands wherein said clock control means includes means for enabling the loading of the result register while execution is delayed pending receipt of a data valid signal.
References Cited (Backward Citations)
US3840861A
Cited
US3839705A
Cited
US4008462A
Cited
US4080648A
Cited
US4075687A
Cited
US4251862A
Cited
US4179736A
Cited
US4325121A
Cited
US4459666A
Cited
US4390946A
Cited
US4586127A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-08-03 | 1991-02-02 | 1991-08-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-08-03 | 1995-02-02 | 1995-08-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-08-03 | 1999-02-02 | 1999-08-04 | $7700.00 | Window Closed / Lapsed |