Data processor including microprogram control means

Claim 2

A microprogram controller for controlling the execution of an instruction by a programmable data processor in response to operation code information contained in an instruction provided to said controller from said processor, comprising: a. a first addressable memory for storing first and second types of microprogram instructions, each of said types containing control data, said first type further containing address information, and said second type further containing data processor control information; b. a second addressable memory for storing control words, each unique to an instruction to be executed by said data processor, said control words containing address information and data processor control information, said second memory being in communication with said data processor and addressable therefrom in response to the operation code information to effect the retrieval of a control word from said second memory; c. control means for selectively providing addressing signals to said first memory to retrieve a microprogram instruction therefrom, said control means including, 1. testing means responsive to the operation code information provided by said data processor and to the control data contained within a previously retrieved one of said first and second types of microprogram instructions for generating address control signals to be utilized in a subsequent accessing of said first memory, 2. address transfer means including an indexable counter, said transfer means being in communication with said first and second memories and receiving the addrsss information contained in a control word previously retrieved from said second memory and that address information and control data contained in the one of said first and second types of microprogram instructions previously retrieved from said first memory, said address transfer means, in a first instance, being selectively responsive to said address control signals and to said control data contained in a previously retrieved first type of microprogram instruction to select and transfer said address information contained in said previously retrieved first type of microprogram instruction and said previously retrieved control word to said memory as said addressing signals, and in a second instance, stepping said indexable counter and transferring an address therefrom as said addressing signals to said first memory in response to control data applied to said testing means and contained in a previously retrieved second type of microprogram instruction; and d. means in communication with said first and second memories for selectively providing control signals for controlling said data processor in accordance with the data processor control information contained in said previously retrieved control word and the data processor control information and control data contained in a previously retrieved second type of microprogram instruction.

Claim 3

a second addressable memory for storing control words, each unique to an instruction to be executed by said data processor, said control words containing address information and data processing unit control information, said second memory being in communication with said data processing unit and addressable therefrom in response to said operation code portion to effect the retrieval of a control word from said second memory,

Claim 4

a second addressable memory for storing control words, each unique to an instruction to be executed by said data processor, said control words containing address information and data processing unit control information, said second memory being in communication with said data processing unit and addressable therefrom in response to said operation code portion to effect the retrieval of a control word from said second memory,

Claim 5

In a programmable data processor the combination comprising: a. a data processing unit including an addressable store for retaining instructions to be executed by said data processing unit, the instructions having at least an operation code portion defining the instructions; b. a microprogram controller in communication with said data processing unit for controlling the execution of instructions in said processing unit, said microprogram controller comprising,

Claim 6

In a programmable data processor the combination comprising: a. a data processing unit including an addressable store for retaining instructions to be executed by said data processing unit, the instructions having at least an operation code portion defining the instructions; b. a microprogram controller in communication with said data processing unit for controlling the execution of instructions in said processing unit, said microprogram controller comprising,

Claim 7

address transfer means including an indexable counter, said transfer means being in communication with said first and second memories and receiving the addrsss information contained in a control word previously retrieved from said second memory and that address information and control data contained in the one of said first and second types of microprogram instructions previously retrieved from said first memory, said address transfer means, in a first instance, being selectively responsive to said address control signals and to said control data contained in a previously retrieved first type of microprogram instruction to select and transfer said address information contained in said previously retrieved first type of microprogram instruction and said previously retrieved control word to said memory as said addressing signals, and in a second instance, stepping said indexable counter and transferring an address therefrom as said addressing signals to said first memory in response to control data applied to said testing means and contained in a previously retrieved second type of microprogram instruction; and d. means in communication with said first and second memories for selectively providing control signals for controlling said data processor in accordance with the data processor control information contained in said previously retrieved control word and the data processor control information and control data contained in a previously retrieved second type of microprogram instruction.

Claim 8

address transfer means including an indexable counter, said transfer means being in communication with said first and second memories and receiving the addrsss information contained in a control word previously retrieved from said second memory and that address information and control data contained in the one of said first and second types of microprogram instructions previously retrieved from said first memory, said address transfer means, in a first instance, being selectively responsive to said address control signals and to said control data contained in a previously retrieved first type of microprogram instruction to select and transfer said address information contained in said previously retrieved first type of microprogram instruction and said previously retrieved control word to said memory as said addressing signals, and in a second instance, stepping said indexable counter and transferring an address therefrom as said addressing signals to said first memory in response to control data applied to said testing means and contained in a previously retrieved second type of microprogram instruction; and d. means in communication with said first and second memories for selectively providing control signals for controlling said data processor in accordance with the data processor control information contained in said previously retrieved control word and the data processor control information and control data contained in a previously retrieved second type of microprogram instruction.

Claim 9

address transfer means including an indexable counter, said transfer means being in communication with said first and second memories and receiving an address contained in the branch address field of a micro-decode word previously retrieved from said second memory, and the address and data contained in the address and defer branch fields of a second type of microprogram instruction when previously retrieved from said first memory, said address transfer means, in said first instance being selectively responsive to said first address control signal and to the data contained in the defer branch field in a previously retrieved first type of microprogram instruction to select and transfer a branch address from one of the branch address fields of the previously retrieved first type of microprogram instruction and micro-decode word to said first memory as said addressing signals, and in a second instance, responsive to said second address control signal to step said indexable counter and transfer an address therefrom, as said addressing signals to said first memory; and d. means in communication with said first and second memories for selectively providing control signals for controlling said data processor in the execution of an instruction in accordance with data contained in the identification and data pRocessor information fields of a previously retrieved second microprogram instruction and the data contained in a previously retrieved micro-decode word.

Claim 10

address transfer means including an indexable counter, said transfer means being in communication with said first and second memories and receiving an address contained in the branch address field of a micro-decode word previously retrieved from said second memory, and the address and data contained in the address and defer branch fields of a second type of microprogram instruction when previously retrieved from said first memory, said address transfer means, in said first instance being selectively responsive to said first address control signal and to the data contained in the defer branch field in a previously retrieved first type of microprogram instruction to select and transfer a branch address from one of the branch address fields of the previously retrieved first type of microprogram instruction and micro-decode word to said first memory as said addressing signals, and in a second instance, responsive to said second address control signal to step said indexable counter and transfer an address therefrom, as said addressing signals to said first memory; and d. means in communication with said first and second memories for selectively providing control signals for controlling said data processor in the execution of an instruction in accordance with data contained in the identification and data pRocessor information fields of a previously retrieved second microprogram instruction and the data contained in a previously retrieved micro-decode word.

Claim 11

A microprogram controller for providing control signals for controlling a data processor in the execution of instructions, the instructions each containing at least an operation code portion defining the instructions, said microprogram controller comprising: a. a first addressable memory for storing first and second types of microprogram instructions, each of said types containing control data, said first type further containing address information, and said second type further containing data processor control information, said microprogram instructions being grouped into subroutines forming a microprogram; b. a second addressable memory for storing control words, each unique to an instruction to be executed by said data processor, said control words containing address information and data processor control information, said second memory being in communication with said data processor and addressable therefrom in response to the operation code portion to effect the retrievAl of a control word from said second memory; c. testing means responsive to the operation code portion of an instruction provided by said data processor and to the control data contained within a previously retrieved one of said first and second types of microprogram instructions for generating address control signals to be utilized in a subsequent accessing of said first memory; d. address transfer means, including an indexable counter, for selectively providing addressing signals to said first memory, said transfer means being in communication with said first and second memories and receiving the address information contained in a control word previously retrieved from said second memory and that address information and control data contained in the one of said first and second types of microprogram instructions previously retrieved from said second memory, said address transfer means, in a first instance, being selectively responsive to said address control signals and to said control data contained in a previously retrieved first type of microprogram instruction to select and transfer said address information contained in said previously retrieved first type of microprogram instruction and said previously retrieved control word to said memory as said addressing signals, to access a subroutine, and in a second instance stepping said indexable counter and transferring an address therefrom as said addressing signals to said first memory in response to control data applied to said testing means and contained in a previously retrieved second type of microprogram instruction to continue the execution of a subroutine presently being executed; and e. means in communication with said first and second memories for selectively providing control signals for controlling said data processor in accordance with the data processor control information contained in said previously retrieved control word and the data processor control information and control data contained in a previously retrieved second type of microprogram instruction.

Claim 12

A microprogram controller for providing control signals for controlling a data processor in the execution of instructions, the instructions each containing at least an operation code portion defining the instructions, said microprogram controller comprising: a. a first addressable memory for storing first and second types of microprogram instructions, each of said types containing control data, said first type further containing address information, and said second type further containing data processor control information, said microprogram instructions being grouped into subroutines forming a microprogram; b. a second addressable memory for storing control words, each unique to an instruction to be executed by said data processor, said control words containing address information and data processor control information, said second memory being in communication with said data processor and addressable therefrom in response to the operation code portion to effect the retrievAl of a control word from said second memory; c. testing means responsive to the operation code portion of an instruction provided by said data processor and to the control data contained within a previously retrieved one of said first and second types of microprogram instructions for generating address control signals to be utilized in a subsequent accessing of said first memory; d. address transfer means, including an indexable counter, for selectively providing addressing signals to said first memory, said transfer means being in communication with said first and second memories and receiving the address information contained in a control word previously retrieved from said second memory and that address information and control data contained in the one of said first and second types of microprogram instructions previously retrieved from said second memory, said address transfer means, in a first instance, being selectively responsive to said address control signals and to said control data contained in a previously retrieved first type of microprogram instruction to select and transfer said address information contained in said previously retrieved first type of microprogram instruction and said previously retrieved control word to said memory as said addressing signals, to access a subroutine, and in a second instance stepping said indexable counter and transferring an address therefrom as said addressing signals to said first memory in response to control data applied to said testing means and contained in a previously retrieved second type of microprogram instruction to continue the execution of a subroutine presently being executed; and e. means in communication with said first and second memories for selectively providing control signals for controlling said data processor in accordance with the data processor control information contained in said previously retrieved control word and the data processor control information and control data contained in a previously retrieved second type of microprogram instruction.

Claim 13

control means for selectively providing addressing signals to said first memory to retrieve a microprogram instruction therefrom, said control means including, test logic responsive to the operation code portion of an instruction from said data processing unit and to the control data contained within a previously retrieved one of said first and second types of microprogram instructions for generating address control signals to be utilized in a subsequent accessing of said first memory, an address transfer means including a serial parallel counter for providing said addressing signals to said first memory, said transfer means being in communication with said first and second memories and receiving the address information contained in a control word previously retrieved from said second memory and that address information and control data contained in the one of said first and second types of microprogram instructions previously retrieved from said first memory, said address transfer means, in a first instance, being selectively responsive to said address control signals and to said control data contained in a previously retrieved first type of microprogram instruction to select and transfer said address information into said serial parallel counter to provide said address signals to said memory in accordance with the address information contained in said previously retrieved first type of microprogram instruction and said previously retrieved control word, and in a second instance, stepping said serial parallel counter and transferring an address therefrom as said addressing signals to said first memory in response to control data applied to said test logic and contained in a previously retrieved second type of microprogram instruction, and

Claim 14

control means for selectively providing addressing signals to said first memory to retrieve a microprogram instruction therefrom, said control means including, test logic responsive to the operation code portion of an instruction from said data processing unit and to the control data contained within a previously retrieved one of said first and second types of microprogram instructions for generating address control signals to be utilized in a subsequent accessing of said first memory, an address transfer means including a serial parallel counter for providing said addressing signals to said first memory, said transfer means being in communication with said first and second memories and receiving the address information contained in a control word previously retrieved from said second memory and that address information and control data contained in the one of said first and second types of microprogram instructions previously retrieved from said first memory, said address transfer means, in a first instance, being selectively responsive to said address control signals and to said control data contained in a previously retrieved first type of microprogram instruction to select and transfer said address information into said serial parallel counter to provide said address signals to said memory in accordance with the address information contained in said previously retrieved first type of microprogram instruction and said previously retrieved control word, and in a second instance, stepping said serial parallel counter and transferring an address therefrom as said addressing signals to said first memory in response to control data applied to said test logic and contained in a previously retrieved second type of microprogram instruction, and

Claim 15

A microprogram controller as recited in claim 3 wherein said second memory includes a register for receiving the operation code portion of an instruction from said data processor for addressing said second memory.

Claim 16

means in communication with said first and second memories for selectively providing control signals for controlling said data processing unit in the execution of an instruction in accordance with the data processor control information contained in said previously retrieved control word and the data processor control information and control data contained in a previously retrieved second type of microprogram instruction.

Claim 17

means in communication with said first and second memories for selectively providing control signals for controlling said data processing unit in the execution of an instruction in accordance with the data processor control information contained in said previously retrieved control word and the data processor control information and control data contained in a previously retrieved second type of microprogram instruction.

Claim 18

In a data processing system of the type including a programmable data processor, the combination comprising: a. a processing unit, including an addressable store, for executing instructions retrieved from said store in accordance with control signals applied to said processing unit, the instructions each having at least an operation code portion to be utilized as an address; b. a first read only memory for storing first and second types of microprogram instructions, each of said types containing control data, said first type further containing address information, and said second type further containing processing unit control information; c. a second read only memory for storing control words, each unique to an instruction to be executed by said processing unit, said control words containing address information and processing unit control information; d. a register in communication with said processing unit and said second read only memory for receiving the operation code portions of an instruction to be executed by said processing unit and addressing said second read only memory to retrieve a control word therefrom; e. a serial parallel counter for providing addressing signals to said first read only memory to retrieve a microprogram instruction from said first read only memory in response to address control signals applied thereto; f. testing means responsive to the operation code portion of an instruction to be executed by said processing unit and to the control data contained in a previously retrieved one of said first and second types of microprogram instructions for providing said address control signals to said serial parallel counter to be used in a subsequent accessing of said fiRst read only memory; g. a multiplexer in communication with said serial parallel counter and with said first and second read only memories and receiving the address information contained in a control word previously retrieved from said second memory and that address information and control data contained in the one of said first and second types of microprogram instructions previously retrieved from said first read only memory, in a first instance, said serial parallel counter being selectively responsive to said address control signals and said multiplexer being selectively responsive to said control data contained in a previously retrieved first type of microprogram instruction to select and transfer said address information contained in said previously retrieved first type of microprogram instruction and said previously retrieved control word in parallel through said serial parallel counter as said addressing signals to said first read only memory, and in a second instance, stepping said serial parallel counter and transferring an address therefrom as said addressing signals to said first memory in response to control data applied to said testing means and contained in a previously retrieved second type of microprogram instruction; and h. means in communication with said first and second read only memories for selectively providing said control signals to said processing unit for controlling said processing unit in accordance with the data processor control information contained in said previously retrieved control word and the data processor control information and control data contained in a previously retrieved second type of microprogram instruction.

Claim 19

In a data processing system of the type including a programmable data processor, the combination comprising: a. a processing unit, including an addressable store, for executing instructions retrieved from said store in accordance with control signals applied to said processing unit, the instructions each having at least an operation code portion to be utilized as an address; b. a first read only memory for storing first and second types of microprogram instructions, each of said types containing control data, said first type further containing address information, and said second type further containing processing unit control information; c. a second read only memory for storing control words, each unique to an instruction to be executed by said processing unit, said control words containing address information and processing unit control information; d. a register in communication with said processing unit and said second read only memory for receiving the operation code portions of an instruction to be executed by said processing unit and addressing said second read only memory to retrieve a control word therefrom; e. a serial parallel counter for providing addressing signals to said first read only memory to retrieve a microprogram instruction from said first read only memory in response to address control signals applied thereto; f. testing means responsive to the operation code portion of an instruction to be executed by said processing unit and to the control data contained in a previously retrieved one of said first and second types of microprogram instructions for providing said address control signals to said serial parallel counter to be used in a subsequent accessing of said fiRst read only memory; g. a multiplexer in communication with said serial parallel counter and with said first and second read only memories and receiving the address information contained in a control word previously retrieved from said second memory and that address information and control data contained in the one of said first and second types of microprogram instructions previously retrieved from said first read only memory, in a first instance, said serial parallel counter being selectively responsive to said address control signals and said multiplexer being selectively responsive to said control data contained in a previously retrieved first type of microprogram instruction to select and transfer said address information contained in said previously retrieved first type of microprogram instruction and said previously retrieved control word in parallel through said serial parallel counter as said addressing signals to said first read only memory, and in a second instance, stepping said serial parallel counter and transferring an address therefrom as said addressing signals to said first memory in response to control data applied to said testing means and contained in a previously retrieved second type of microprogram instruction; and h. means in communication with said first and second read only memories for selectively providing said control signals to said processing unit for controlling said processing unit in accordance with the data processor control information contained in said previously retrieved control word and the data processor control information and control data contained in a previously retrieved second type of microprogram instruction.

Claim 20

A microprogram controller for controlling operations in an external device, comprising: a. a first addressable memory for storing first and second types of microprogram instructions, each of said types containing control data, said first type further containing address information, and said second type further containing external device control information; b. a second addressable memory for storing control words, each unique to operations to be controlled in said external device, said second memory being addressable from said external device in accordance with coded information specifying an operation to be performed by said external device to effect the retrieval of a control word from said second memory; c. test logic responsive to the coded information from said external device and to the control data contained within a previously retrieved one of said first and second types of microprogram instructions for generating address control signals to be utilized in a subsequent accessing of said first memory; d. a serial parallel counter for providing addressing signals to said first memory to retrieve a microprogram instruction from said first memory in response to said address control signals from said test logic; e. transfer means in communication with said serial parallel counter and with said first and second memories and receiving the address information contained in a control word previously retrieved from said second memory and that address information and control data contained in the one of said first and second types of microprogram instructions previously retrieved from said first memory, in a first instance, said serial parallel counter being selectively responsive to said address control signals and said transfer means being selectively responsive to said control data contained in a previously retrieved first type of microprogram instruction to select and transfer said address information contained in said previously retrieved first type of microprogram instruction and said previously retrieved control word in parallel through said serial parallel counter as said addressing signals to said first memory, and in a second instance, incrementing said serial parallel counter by one to sequentially address said first memory, said address control signals in said second instanCe being generated in accordance with the control data contained in a previously retrieved second type of microprogram instruction and applied to said test logic; and, f. multiplexer means in communication with said first and second memories for selectively providing control signals for controlling operations in said external device in accordance with the external device control information contained in said previously retrieved control word and the external device control information and control data contained in a previously retrieved second type of microprogram instruction.

Claim 21

A microprogram controller for controlling operations in an external device, comprising: a. a first addressable memory for storing first and second types of microprogram instructions, each of said types containing control data, said first type further containing address information, and said second type further containing external device control information; b. a second addressable memory for storing control words, each unique to operations to be controlled in said external device, said second memory being addressable from said external device in accordance with coded information specifying an operation to be performed by said external device to effect the retrieval of a control word from said second memory; c. test logic responsive to the coded information from said external device and to the control data contained within a previously retrieved one of said first and second types of microprogram instructions for generating address control signals to be utilized in a subsequent accessing of said first memory; d. a serial parallel counter for providing addressing signals to said first memory to retrieve a microprogram instruction from said first memory in response to said address control signals from said test logic; e. transfer means in communication with said serial parallel counter and with said first and second memories and receiving the address information contained in a control word previously retrieved from said second memory and that address information and control data contained in the one of said first and second types of microprogram instructions previously retrieved from said first memory, in a first instance, said serial parallel counter being selectively responsive to said address control signals and said transfer means being selectively responsive to said control data contained in a previously retrieved first type of microprogram instruction to select and transfer said address information contained in said previously retrieved first type of microprogram instruction and said previously retrieved control word in parallel through said serial parallel counter as said addressing signals to said first memory, and in a second instance, incrementing said serial parallel counter by one to sequentially address said first memory, said address control signals in said second instanCe being generated in accordance with the control data contained in a previously retrieved second type of microprogram instruction and applied to said test logic; and, f. multiplexer means in communication with said first and second memories for selectively providing control signals for controlling operations in said external device in accordance with the external device control information contained in said previously retrieved control word and the external device control information and control data contained in a previously retrieved second type of microprogram instruction.

Claim 22

A microprogram controller for controlling the execution of an instruction by a programmable data processor in response to status conditions generated by said data processor and to an operation code portion contained in an instruction to be executed by said processor, said microprogram controller comprising: a. a first addressable memory for storing first and second types of microprogram instructions, said first type serving as a branch instruction containing an instruction identification field, a bit test field, a defer branch field and a branch address field and said second type serving as a control word containing an instruction identification field, a branch address field, and at least one field containing data processor control information; b. a second addressable memory for storing micro-decode words, each unique to an instruction to be executed by said data processor, said micro-decode words containing a branch address field and at least one field containing data processor control information, said second memory being in communication with said data processor and addressable therefrom in response to the operation code portion to effect the retrieval of a micro-decode word from said second memory; c. control means for selectively providing addressing signals to said first memory to retrieve a microprogram instruction therefrom, said control means including,

Claim 23

A microprogram controller for controlling the execution of an instruction by a programmable data processor in response to status conditions generated by said data processor and to an operation code portion contained in an instruction to be executed by said processor, said microprogram controller comprising: a. a first addressable memory for storing first and second types of microprogram instructions, said first type serving as a branch instruction containing an instruction identification field, a bit test field, a defer branch field and a branch address field and said second type serving as a control word containing an instruction identification field, a branch address field, and at least one field containing data processor control information; b. a second addressable memory for storing micro-decode words, each unique to an instruction to be executed by said data processor, said micro-decode words containing a branch address field and at least one field containing data processor control information, said second memory being in communication with said data processor and addressable therefrom in response to the operation code portion to effect the retrieval of a micro-decode word from said second memory; c. control means for selectively providing addressing signals to said first memory to retrieve a microprogram instruction therefrom, said control means including,